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P4C169-70FM 데이터시트(Datasheet) 1 Page - Pyramid Semiconductor Corporation

부품명 P4C169-70FM
상세내용  ULTRA HIGH SPEED 4K x 4 STATIC CMOS RAMS
PDF  15 Pages
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제조사  PYRAMID [Pyramid Semiconductor Corporation]
홈페이지  http://www.pyramidsemiconductor.com
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 1 page
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1
Document # SRAM107 REV A
Revised October 2005
P4C168, P4C169, P4C170
ULTRA HIGH SPEED 4K x 4
STATIC CMOS RAMS
DESCRIPTION
The P4C168, P4C169 and P4C170 are a family of
16,384-bit ultra high-speed static RAMs organized as 4K
x 4. All three devices have common input/output ports.The
P4C168 enters the standby mode when the chip enable
(CE) control goes HIGH; with CMOS input levels, power
consumption is only 83mW in this mode. Both the P4C169
and the P4C170 offer a fast chip select access time that
is only 67% of the address access time. In addition, the
P4C170 includes an output enable (OE) control to elimi-
nate data bus contention. The RAMs operate from a
single 5V ± 10% tolerance power supply.
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 12/15/20/25/35ns (Commercial)
– 20/25/35/45/55/70ns (P4C168 Military)
Low Power Operation (Commercial)
– 715 mW Active
– 193 mW Standby (TTL Input) P4C168
– 83 mW Standby (CMOS Input) P4C168
Single 5V±10% Power Supply
Fully TTL Compatible, Common I/O Ports
Three Options
– P4C168 Low Power Standby Mode
– P4C169 Fast Chip Select Control
– P4C170 Fast Chip Select, Output Enable
Controls
Standard Pinout (JEDEC Approved)
– P4C168: 20-pin DIP, SOJ, LCC, SOIC,
CERPACK, and Flat Pack
– P4C169: 20-pin DIP and SOIC
– P4C170: 22-pin DIP
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption to a low 715
mW active, 193 mW standby.
The P4C168 and P4C169 are available in 20-pin (P4C170
in 22-pin) 300 mil DIP packages providing excellent
board level densities. The P4C168 is also available in 20-
pin 300 mil SOIC, SOJ, CERPACK, and Flat Pack
packages.
The P4C169 is also available in a 20-pin 300 mil SOIC
package.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
P4C168
P4C169
DIP (P2, C6, D2)
DIP (P2)
SOIC (S2)
SOIC (S2)
SOJ (J2)
CERPACK (F2)
SOLDER SEAL FLAT PACK (FS-2)
P4C170
DIP (P3)
 2 page
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P4C168, P4C169, P4C170
Page 2 of 15
Document # SRAM107 REV A
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
V
CC
Power Supply Pin with
– 0.5 to +7
V
Respect to GND
Terminal Voltage with
– 0.5 to
V
TERM
Respect to GND
V
CC + 0.5
V
(up to 7.0V)
T
A
Operating Temperature
–55 to +125
°C
Symbol
Parameter
Value
Unit
T
BIAS
Temperature Under
– 55 to +125
°C
Bias
T
STG
Storage Temperature
– 65 to +150
°C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
Symbol
Parameter
Conditions Typ. Unit
C
IN
Input Capacitance
V
IN = 0V
5
pF
C
OUT
Output Capacitance V
OUT= 0V
7
pF
RECOMMENDED OPERATING CONDITIONS
CAPACITANCES(4)
(V
CC = 5.0V, TA = 25°C, f = 1.0MHz)
Grade(2)
Commercial
Military
Ambient Temp
0°C to 70°C
–55°C to +125°C
Gnd
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
V
IH
V
IL
V
HC
V
LC
V
OH
I
LI
I
SB
I
SB1
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(CMOS Load)
Input Leakage Current
Output Leakage Current
Dynamic Operating
Current
Standby Power Supply
Current (TTL Input Levels)
P4C168 only
Standby Power
Supply Current
(CMOS Input Levels)
P4C168 only
Input Clamp Diode Voltage
Output Low Voltage
(CMOS Load)
Output High Voltage
(TTL Load)
Parameter
Symbol
Test Conditions
V
CC = Min., IIN = –18 mA
V
CC = Max., VIN = GND to VCC
V
CC = Max., CS = VIH,
V
OUT = GND to VCC
CE
≥ V
IH, VCC = Max., f = Max.,
Outputs Open
CE
≥ V
HC, VCC = Max., f = 0,
Outputs Open
V
IN ≤ VLC or VIN ≥ VHC
Mil.
Comm’l
Mil.
Comm’l
P4C168/169/170
Min
2.2
–0.5(3)
V
CC –0.2
–0.5(3)
2.4
–10
–5
–10
–5
Max
V
CC +0.5
0.8
V
CC +0.5
0.2
+10
+5
+10
+5
Unit
V
V
V
V
–1.2
V
V
CD
I
OL = +8 mA, VCC = Min.
0.4
V
V
OL
I
OLC = +100 µA, VCC = Min.
0.2
V
V
OLC
I
OH = –4 mA, VCC = Min.
V
I
OHC = –100 µA, VCC = Min.
V
CC –0.2
V
V
OHC
µA
I
LO
µA
I
CC
35
mA
15
mA
___
___
V
CC = Max., f = Max., Outputs Open
130
mA
___
DC ELECTRICAL CHARACTERISTICS
 3 page
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P4C168, P4C169, P4C170
Page 3 of 15
Document # SRAM107 REV A
AC CHARACTERISTICS—READ CYCLE
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)
§ P4C168 only
† P4C170 only
‡ Chip Select/Deselect for P4C169 and P4C170
Min Max Min Max Min Max Min Max Min Max
tRC
Read Cycle Time
12
15
20
25
35
ns
tAA
Address Access Time
12
15
20
25
35
ns
tAC§
Chip Enable Access Time
12
15
20
25
35
ns
tAC‡
Chip Select Access Time
8
9
12
15
20
ns
tOH
Output Hold from Address Change
22222
ns
tLZ‡
Chip Enable to Output in Low Z
22222
ns
tHZ†
Chip Disable to Output in High Z
7
8
9
10
15
ns
tOE†
Output Enable to Data Valid
8
10
12
15
15
ns
tOLZ†
Output Enable to Output in Low Z
00000
ns
tOHZ†
Output Disable to Output in High Z
6
7
9
11
15
ns
tRCS
Read Command Setup Time
00000
ns
tRCH
Read Command Hold Time
00000
ns
tPU§
Chip Enable to Power Up Time
00000
ns
tPD§
Chip Disable to Power Down Time
12
15
20
25
35
ns
Sym
Parameter
Unit
-35
-12
-15
-20
-25
AC CHARACTERISTICS—READ CYCLE (CONTINUED)
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max
tRC
Read Cycle Time
45
55
70
ns
tAA
Address Access Time
45
55
70
ns
tAC§
Chip Enable Access Time
45
55
70
ns
tOH
Output Hold from Address Change
2
2
2
ns
tLZ‡
Chip Enable to Output in Low Z
2
2
2
ns
tHZ†
Chip Disable to Output in High Z
25
25
30
ns
tRCS
Read Command Setup Time
0
0
0
ns
tRCH
Read Command Hold Time
0
0
0
ns
tPU§
Chip Enable to Power Up Time
0
0
0
ns
tPD§
Chip Disable to Power Down Time
45
55
70
ns
Sym
Parameter
Unit
-45
-55
-70
 4 page
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P4C168, P4C169, P4C170
Page 4 of 15
Document # SRAM107 REV A
Notes:
7. ADDRESS must be valid prior to, or coincident with CE/CS transition
low. For Fast CS, t
AA must still be met.
8. Transition is measured ±200mV from steady state voltage prior to
change, with loading as specified in Figure 1.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF READ CYCLE NO. 2 (CE
CE
CE
CE
CE/CS
CS
CS
CS
CS CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3—P4C170 ONLY (OE
OE
OE
OE
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (ADDRESS CONTROLLED)(5,6)
Notes:
5. WE is HIGH for READ cycle.
6. CE/CS and OE are LOW for READ cycle.
 5 page
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P4C168, P4C169, P4C170
Page 5 of 15
Document # SRAM107 REV A
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max Min Max Min Max
tWC
Write Cycle Time
12
15
18
20
30
ns
tcw
Chip Enable Time to End of Write
1215182030
ns
tAW
Address Valid to End of Write
1215182030
ns
tAS
Address Set-up Time
00000
ns
tWP
Write Pulse Width
1215182030
ns
tAH
Address Hold Time
00000
ns
tDW
Data Valid to End of Write
7
8
10
10
15
ns
tDH
Data Hold Time
00000
ns
tWZ
Write Enable to Output in High Z
4567
13
ns
tOW
Output Active from End of Write
00000
ns
Sym
Parameter
Unit
-35
-12
-15
-20
-25
AC ELECTRICAL CHARACTERISTICS - WRITE CYCLE (CONTINUED)
(V
CC = 5V ± 10%, All Temperature Ranges)
(2)
Min Max Min Max Min Max
tWC
Write Cycle Time
45
55
70
ns
tcw
Chip Enable Time to End of Write
40
50
60
ns
tAW
Address Valid to End of Write
40
50
60
ns
tAS
Address Set-up Time
0
0
0
ns
tWP
Write Pulse Width
40
50
60
ns
tAH
Address Hold Time
0
0
0
ns
tDW
Data Valid to End of Write
20
20
25
ns
tDH
Data Hold Time
3
3
3
ns
tWZ
Write Enable to Output in High Z
20
25
30
ns
tOW
Output Active from End of Write
0
0
0
ns
Sym
Parameter
Unit
-45
-55
-70
 6 page
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P4C168, P4C169, P4C170
Page 6 of 15
Document # SRAM107 REV A
Mode
CE
CE
CE
CE
CE (CS
CS
CS
CS
CS)
WE
WE
WE
WE
WE
Output
Standby (Deselect)
H
X
High Z
Read
L
H
D
OUT
Write
L
L
High Z
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
CE
CE
CE
CE/CS
CS
CS
CS
CS CONTROLLED)(10)
TRUTH TABLES
P4C168 (P4C169)
P4C170
Mode
CE
CE
CE
CE
CE
WE
WE
WE
WE
WE
OE
OE
OE
OE
OE
Output
Deselect
H
X
X
High Z
Read
L
H
L
D
OUT
Output Inhibit
L
H
H
High Z
Write
L
L
X
High Z
Notes:
10. CE/CS and WE must be LOW for WRITE cycle.
11. If CE/CS goes HIGH simultaneously with WE HIGH, the output
remains in a high impedance state.
12. Write Cycle Time is measured from the last valid address to the first
transitioning address.
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
WE
WE
WE
WE CONTROLLED)(10)
 7 page
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P4C168, P4C169, P4C170
Page 7 of 15
Document # SRAM107 REV A
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C168, P4C169 AND P4C170
care must be taken when testing these devices; an inadequate setup
can cause a normal functioning part to be rejected as faulty. Long high-
inductance leads that cause supply bounce must be avoided by bringing
the V
CC and ground planes directly up to the contactor fingers. A high
frequency capacitor of 0.01 µF is also required between V
CC and ground.
Figure 1. Output Load
Figure 2. Thevenin Equivalent
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
1.5V
Output Timing Reference Level
1.5V
Output Load
See Figures 1 and 2
AC TEST CONDITIONS
To avoid signal reflections, proper termination must be used; for
example, a 50
Ω test environment should be terminated into a 50Ω load
with 1.73V (Thevenin Voltage) at the comparator input, and a 116
resistor must be used in series with D
OUT to match 166Ω (Thevenin
Resistance).
LCC PIN CONFIGURATION
LCC (L9)
 8 page
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P4C168, P4C169, P4C170
Page 8 of 15
Document # SRAM107 REV A
ORDERING INFORMATION
SELECTION GUIDE
The P4C168, P4C169 and P4C170 are available in the following temperature, speed and package options.
† P4C168 and P4C169 only.
†† P4C168
* Military temperature range with MIL-STD-883, Class B processing.
N/A = Not available
12
15
20
25
35
Plastic DIP
-12PC
-15PC
-20PC
-25PC
N/A
Plastic SOIC†
-12SC
-15SC
-20SC
-25SC
N/A
Plastic SOJ††
-12JC
-15JC
-20JC
-25JC
N/A
LCC
N/A
-15LM
-20LM
-25LM
-35LM
CERDIP
N/A
-15DM
-20DM
-25DM
-35DM
Side Brazed DIP
N/A
-15CM
-20CM
-25CM
-35CM
CERPACK
N/A
-15FM
-20FM
-25FM
-35FM
Solder Seal Flat Pack
N/A
-15FSM
-20FSM
-25FSM
-35FSM
LCC
N/A
-15LMB
-20LMB
-25LMB
-35LMB
CERDIP
N/A
-15DMB
-20DMB
-25DMB
-35DMB
Side Brazed DIP
N/A
-15CMB
-20CMB
-25CMB
-35CMB
CERPACK
N/A
-15FMB
-20FMB
-25FMB
-35FMB
Solder Seal Flat Pack
N/A
-15FSMB
-20FSMB
-25FSMB
-35FSMB
Military
Processed*
(P4C168 only)
Speed
Temperature
Range
Package
Commercial
Temperature
Military
Temperature
(P4C168 only)
 9 page
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P4C168, P4C169, P4C170
Page 9 of 15
Document # SRAM107 REV A
SELECTION GUIDE (CONTINUED)
* Military temperature range with MIL-STD-883, Class B processing.
45
55
70
LCC
-45LM
-55LM
-70LM
CERDIP
-45DM
-55DM
-70DM
Side Brazed DIP
-45CM
-55CM
-70CM
CERPACK
-45FM
-55FM
-70FM
Solder Seal Flat Pack
-45FSM
-55FSM
-70FSM
LCC
-45LMB
-55LMB
-70LMB
CERDIP
-45DMB
-55DMB
-70DMB
Side Brazed DIP
-45CMB
-55CMB
-70CMB
CERPACK
-45FMB
-55FMB
-70FMB
Solder Seal Flat Pack
-55FSMB
-55FSMB
-70FSMB
Military
Processed*
(P4C168 only)
Speed
Temperature
Range
Package
Military
Temperature
(P4C168 only)
 10 page
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P4C168, P4C169, P4C170
Page 10 of 15
Document # SRAM107 REV A
CERPACK CERAMIC FLAT PACKAGE
Pkg #
# Pins
Symbol
Min
Max
A
0.060
0.090
b
0.015
0.022
c
0.004
0.009
D-
0.530
E
0.305
0.355
e
k
0.005
0.018
L
0.250
0.370
Q
0.026
0.045
S-
0.085
S1
0.005
-
F2
20
0.050 BSC
SIDE BRAZED DUAL IN-LINE PACKAGE
Pkg #
# Pins
Symbol
Min
Max
A-
0.200
b
0.014
0.026
b2
0.045
0.065
C
0.008
0.018
D-
1.060
E
0.220
0.310
eA
e
L
0.125
0.200
Q
0.015
0.070
S1
0.005
-
S2
0.005
-
C6
20 (300 mil)
0.300 BSC
0.100 BSC




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