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ADDI7004BBCZ 데이터시트(Datasheet) 1 Page - Analog Devices

부품명 ADDI7004BBCZ
상세내용  Quad-Channel, HD Image Signal Processor with Precision Timing Core
PDF  2 Pages
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제조사  AD [Analog Devices]
홈페이지  http://www.analog.com
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Quad-Channel, HD Image Signal Processor
with Precision Timing Core
Data Sheet
ADDI7004
Rev. SpD
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2008–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
Support for CCD and CMOS image sensors
4 AFE channels
1.8 V analog and digital core supply voltage
Serial data output with reduced range LVDS outputs
Differential analog inputs
CDS or SHA configuration (CDS bypass) with
−3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 72 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Precision Timing core with 220 ps resolution @ 72 MHz
APPLICATIONS
Digital video cameras
Digital still cameras
Medical Imaging
High speed industrial cameras
GENERAL DESCRIPTION
The ADDI7004 is a highly integrated, quad-channel, HD image
signal processor for high speed imaging applications. Each channel
is specified at pixel rates of up to 72 MHz and consists of a complete
analog front end (AFE) with ADC conversion. The Precision
Timing™ core allows adjustment of the correlated double sampler
(CDS) and sample-and-hold amplifier (SHA) clocks with 220 ps
resolution at 72 MHz operation. The ADDI7004 also contains
a reduced range low voltage differential signaling (LVDS) inter-
face for the dual-channel data outputs.
Each analog front end includes black level clamping, a CDS/SHA,
a VGA, and a 72 MHz, 14-bit analog-to-digital converter (ADC).
Operation is programmed using a 3-wire serial interface.
Packaged in a space-saving, 6 mm × 6 mm, 76-ball BGA, the
ADDI7004 is specified over an operating temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
DOUT0P
DOUT0N
DOUT1P
DOUT1N
DOUT2P
DOUT2N
DOUT3P
DOUT3N
TCLK0P
TCLK0N
TCLK1P
TCLK1N
DOUT4P
DOUT4N
DOUT5P
DOUT5N
DOUT6P
DOUT6N
DOUT7P
DOUT7N
INP_B
INM_B
INP_C
INM_C
INP_D
SHP
SHD
CLPOB
PBLK
DCR
INM_D
AFE2
AFE3
AFE4
INP_A
INM_A
–3dB, 0dB, +3dB, +6dB
CDS/
SHA
VGA
6dB ~ 42dB
CLAMP
VREF
ADC
AFE1
REDUCED
RANGE
LVDS
INTERFACE
VD
HD
SDATA
SCK
CLI
RSTB
SL
Precision
Timing
CORE
SYNC
GENERATOR
INTERNAL CLOCKS
INTERNAL
REGISTERS
ADDI7004
NOTES
1. THE CIRCUITRY FOR AFE1 TO AFE4 IS IDENTICAL.
Figure 1.
For more information on the ADDI7004, email Analog Devices, Inc., at afe.ccd@analog.com.
 2 page
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ADDI7004
Data Sheet
Rev. SpD | Page 2 of 2
NOTES
©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07799F-0-4/13(SpD)




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