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MC74VHC4316_11 데이터시트(Datasheet) 1 Page - ON Semiconductor

부품명 MC74VHC4316_11
상세내용  Digital Power Supplies
PDF  12 Pages
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제조사  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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 1 page
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© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 3
1
Publication Order Number:
MC74VHC4316/D
MC74VHC4316
Quad Analog Switch/
Multiplexer/Demultiplexer
with Separate Analog and
Digital Power Supplies
High−Performance Silicon−Gate CMOS
The MC74VHC4316 utilizes silicon−gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low
OFF−channel leakage current. This bilateral switch/multiplexer/
demultiplexer controls analog and digital voltages that may vary
across the full analog power−supply range (from VCC to VEE).
The VHC4316 is similar in function to the metal−gate CMOS
MC14016 and MC14066, and to the High−Speed CMOS HC4066A.
Each device has four independent switches. The device control and
Enable inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs. The device
has been designed so that the ON resistances (RON) are much more
linear over input voltage than RON of metal−gate CMOS analog
switches. Logic−level translators are provided so that the On/Off
Control and Enable logic−level voltages need only be VCC and GND,
while the switch is passing signals ranging between VCC and VEE.
When the Enable pin (active−low) is high, all four analog switches are
turned off.
Features
Logic−Level Translator for On/Off Control and Enable Inputs
Fast Switching and Propagation Speeds
High ON/OFF Output Voltage Ratio
Diode Protection on All Inputs/Outputs
Analog Power−Supply Voltage Range (VCC − VEE) = 2.0 to 12.0 V
Digital (Control) Power−Supply Voltage Range
(VCC − GND) = 2.0 V to 6.0 V, Independent of VEE
Improved Linearity of ON Resistance
Chip Complexity: 66 FETs or 16.5 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
1
16
1
16
VHC4316G
AWLYWW
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
TSSOP−16
DT SUFFIX
CASE 948F
1
16
VHC
4316
ALYWG
G
1
16
(Note: Microdot may be in either location)
Device
Package
Shipping
ORDERING INFORMATION
48 Units / Rail
MC74VHC4316DG
SOIC−16
(Pb−Free)
MC74VHC4316DTG
TSSOP16
(Pb−Free)
96 Units / Rail
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
SOIC−16
(Pb−Free)
MC74VHC4316DR2G
2500/Tape&Reel
MC74VHC4316DTR2G TSSOP16
(Pb−Free)
2500/Tape&Reel
 2 page
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2
Figure 1. Pin Assignment
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
YD
XD
D ON/OFF
CONTROL
A ON/OFF
CONTROL
VCC
VEE
XC
YC
XB
YB
YA
XA
GND
ENABLE
C ON/OFF
CONTROL
B ON/OFF
CONTROL
FUNCTION TABLE
Inputs
State of Analog
Switch
Enable
On/Off Control
L
L
H
H
L
X
On
Off
Off
X = Don’t Care.
Figure 2. Logic Diagram
XA
A ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
ANALOG
OUTPUTS/INPUTS
PIN 16 = VCC
PIN 8 = GND
PIN 9 = VEE
GND
≥ VEE
2
YA
1
15
XB
B ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
3
YB
4
5
XC
C ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
11
YC
10
6
XD
D ON/OFF CONTROL
ANALOG
SWITCH
LEVEL
TRANSLATOR
12
YD
13
14
ENABLE
7
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
 3 page
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3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
Positive DC Supply Voltage
(Ref. to GND)
(Ref. to VEE)
– 0.5 to + 7.0
– 0.5 to + 14.0
V
VEE
Negative DC Supply Voltage (Ref. to GND)
– 7.0 to + 0.5
V
VIS
Analog Input Voltage
VEE – 0.5
to VCC + 0.5
V
Vin
DC Input Voltage (Ref. to GND)
– 0.5 to VCC + 0.5
V
I
DC Current Into or Out of Any Pin
± 25
mA
PD
Power Dissipation in Still Air
SOIC Package*
TSSOP Package*
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*Derating − SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: − 6.1 mW/°C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor
High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
Positive DC Supply Voltage (Ref. to GND)
2.0
6.0
V
VEE
Negative DC Supply Voltage (Ref. to GND)
– 6.0
GND
V
VIS
Analog Input Voltage
VEE
VCC
V
Vin
Digital Input Voltage (Ref. to GND)
GND
VCC
V
VIO*
Static or Dynamic Voltage Across Switch
1.2
V
TA
Operating Temperature, All Package Types
– 55
+ 125
°C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Control or Enable Inputs)
VCC = 3.0 V
(Figure 10)
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
600
500
400
ns
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
 4 page
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4
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
– 55 to
25°C
v 85°C
v 125°C
VIH
Minimum High−Level Voltage, Control
or Enable Inputs
Ron = Per Spec
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum Low−Level Voltage, Control
or Enable Inputs
Ron = Per Spec
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
Iin
Maximum Input Leakage Current,
Control or Enable Inputs
Vin = VCC or GND
VEE = – 6.0 V
6.0
± 0.1
± 1.0
± 1.0
mA
ICC
Maximum Quiescent Supply Current
(per Package)
Vin = VCC or GND
VIO = 0 V
VEE = GND
VEE = – 6.0
6.0
6.0
2
4
20
40
40
160
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE)
Symbol
Parameter
Test Conditions
VCC
V
VEE
V
Guaranteed Limit
Unit
– 55 to
25°C
v 85°C
v 125°C
Ron
Maximum “ON” Resistance
Vin = VIH
VIS = VCC to VEE
IS v 2.0 mA
2.0*
4 5
4.5
6.0
0.0
0.0
− 4.5
− 6.0
160
90
90
200
110
110
240
130
130
W
Vin = VIH
VIS = VCC or VEE (Endpoints)
IS v 2.0 mA
2.0
4.5
4.5
6.0
0.0
0.0
− 4.5
− 6.0
90
70
70
115
90
90
140
105
105
DRon
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = VIH
VIS = 1/2 (VCC − VEE)
IS v 2.0 mA
2.0
4.5
4.5
6.0
0.0
0.0
– 4.5
– 6.0
20
15
15
25
20
20
30
25
25
W
Ioff
Maximum Off−Channel
Leakage Current, Any One
Channel
Vin = VIL
VIO = VCC or VEE
Switch Off (Figure 3)
6.0
– 6.0
0.1
0.5
1.0
mA
Ion
Maximum On−Channel
Leakage Current, Any One
Channel
Vin = VIH
VIS = VCC or VEE
(Figure 4)
6.0
– 6.0
0.1
0.5
1.0
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
*At supply voltage (VCC − VEE) approaching 2.0 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage
operation, it is recommended that these devices only be used to control digital signals.
 5 page
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5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to
25°C
v 85°C
v 125°C
tPLH,
tPHL
Maximum Propagation Delay, Analog Input to Analog Output
(Figures 8 and 9)
2.0
4.5
6.0
40
6
5
50
8
7
60
9
8
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)
2.0
4.5
6.0
130
40
30
160
50
40
200
60
50
ns
tPZL,
tPZH
Maximum Propagation Delay, Control or Enable to Analog Output
(Figures 10 and 11)
2.0
4.5
6.0
140
40
30
175
50
40
250
60
50
ns
C
Maximum Capacitance
ON/OFF Control
and Enable Inputs
10
10
10
pF
Control Input = GND
Analog I/O
Feedthrough
35
1.0
35
1.0
35
1.0
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Switch) (Figure 13)*
Typical @ 25°C, VCC = 5.0 V
pF
15
*Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Symbol
Parameter
Test Conditions
VCC
V
VEE
V
Limit*
25°C
Unit
BW
Maximum On–Channel Bandwidth
or
Minimum Frequency Response
(Figure 5)
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequency Until dB Meter
Reads – 3 dB
RL = 50 W, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
150
160
160
MHz
Off–Channel Feedthrough
Isolation
(Figure 6)
fin  Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 50
– 50
– 50
dB
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 40
– 40
– 40
Feedthrough Noise, Control to
Switch
(Figure 7)
Vin v 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 W, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
60
130
200
mVPP
RL = 10 kW, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
30
65
100
Crosstalk Between Any Two
Switches
(Figure 12)
fin  Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 W, CL = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 70
– 70
– 70
dB
fin = 1.0 MHz, RL = 50 W, CL = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 80
– 80
– 80
THD
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kW, CL = 50 pF
THD = THDMeasured − THDSource
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
0.10
0.06
0.04
%
*Limits not tested. Determined by design and verified by qualification.
 6 page
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MC74VHC4316
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6
Figure 1. On Resistance Test Set−Up
PLOTTER
MINI COMPUTER
PROGRAMMABLE
POWER
SUPPLY
DC ANALYZER
VCC
+
-
ANALOG IN
COMMON OUT
GND
DEVICE
UNDER TEST
VEE
 7 page
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7
Figure 2. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Figure 3. Maximum On Channel Leakage Current,
Test Set−Up
OFF
16
VCC
VEE
A
VCC
VEE
VCC
O/I
7
8
9
SELECTED
CONTROL
INPUT
VIL
ON
16
VCC
N/C
A
VEE
VCC
VEE
7
8
9
SELECTED
CONTROL
INPUT
VIH
Figure 4. Maximum On−Channel Bandwidth
Test Set−Up
ON
16
VCC
0.1
mF
CL*
fin
TO dB
METER
*Includes all probe and jig capacitance.
RL
RL
VEE
7
8
9
SELECTED
CONTROL
INPUT
VCC
Figure 5. Off−Channel Feedthrough Isolation,
Test Set−Up
OFF
16
VCC
0.1
mF
CL*
fin
TO dB
METER
*Includes all probe and jig capacitance.
RL
VEE
7
8
9
SELECTED
CONTROL
INPUT
RL
VCC
Figure 6. Feedthrough Noise, Control to Analog Out,
Test Set−Up
16
VCC
*Includes all probe and jig capacitance.
ON/OFF
CONTROL
RL
SELECTED
CONTROL
INPUT
VEE
7
8
9
CL*
TEST
POINT
RL
VCC
GND
ANALOG IN
ANALOG OUT
50%
tPLH
tPHL
50%
Figure 7. Propagation Delays, Analog In to
Analog Out
VIS
 8 page
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8
POSITIONWHEN TESTING tPLZ AND tPZL
Figure 8. Propagation Delay Test Set−Up
ON
16
VCC
*Includes all probe and jig capacitance.
TEST
POINT
ANALOG O/I
ANALOG I/O
50 pF*
SELECTED
CONTROL
INPUT
VCC
Figure 9. Propagation Delay, ON/OFF Control
to Analog Out
ON/OFF
VCC
TEST
POINT
16
VCC
1 k
W
POSITIONWHEN TESTING tPHZ AND tPZH
50 pF*
1
2
1
2
Figure 10. Propagation Delay Test Set−Up
1
2
Figure 11. Crosstalk Between Any Two Switches,
Test Set−Up (Adjacent Channels Used)
RL
ON
16
*Includes all probe and jig capacitance.
OFF
RL
VIS
fin
0.1
mF
Figure 12. Power Dissipation Capacitance
Test Set−Up
16
VCC
N/C
ON/OFF
A
N/C
SELECTED
CONTROL
INPUT
CONTROL
ON
16
VCC
10
mF
CL*
fin
RL
TO
DISTORTION
METER
*Includes all probe and jig capacitance.
VOS
VIS
SELECTED
CONTROL
INPUT
VCC
Figure 13. Total Harmonic Distortion, Test Set−Up
7
8
9
*Includes all probe and jig capacitance.
8
9
CONTROL
OR
ENABLE
VCC
7
8
9
VEE
CL*
CL*
RL
SELECTED
CONTROL
INPUT
VCC
TEST
POINT
ANALOG I/O
7
8
9
VEE
7
8
9
VEE
50%
50%
90%
10%
tPZL
tPLZ
tPZH
tPHZ
HIGH
IMPEDANCE
VOL
VOH
HIGH
IMPEDANCE
VCC
GND
50%
ANALOG
OUT
CONTROL
ENABLE
tr
tf
 9 page
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9
APPLICATIONS INFORMATION
0
-10
-20
-30
-40
-50
- 100
1.0
2.0
FREQUENCY (kHz)
-60
-70
-80
-90
FUNDAMENTAL FREQUENCY
DEVICE
SOURCE
Figure 14. Plot, Harmonic Distortion
3.0
The Enable and Control pins should be at VCC or GND
logic levels, VCC being recognized as logic high and GND
being recognized as a logic low. Unused analog
inputs/outputs may be left floating (not connected).
However, it is advisable to tie unused analog inputs and
outputs to VCC or VEE through a low value resistor. This
minimizes crosstalk and feedthrough noise that may be
picked up by the unused I/O pins.
The maximum analog voltage swings are determined by
the supply voltages VCC and VEE. The positive peak analog
voltage should not exceed VCC. Similarly, the negative peak
analog voltage should not go below VEE. In the example
below, the difference between VCC and VEE is 12 V.
Therefore, using the configuration in Figure 15, a maximum
analog signal of twelve volts peak−to−peak can be
controlled.
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external diodes (Dx) are
recommended as shown in Figure 16. These diodes should
be small signal, fast turn−on types able to absorb the
maximum anticipated current surges during clipping. An
alternate method would be to replace the Dx diodes with
MOSORBs (MOSORB
t is an acronym for high current
surge protectors). MOSORBs are fast turn−on devices
ideally suited for precise dc protection with no inherent wear
out mechanism.
ANALOG O/I
ON
16
VCC = 6 V
ANALOG I/O
+ 6 V
-6 V
+ 6 V
-6 V
ENABLE CONTROL
INPUTS
(VCC OR GND)
ON
16
VCC
Dx
Dx
VCC
Dx
Figure 15.
Figure 16. Transient Suppressor Application
8
SELECTED
CONTROL
INPUT
Dx
SELECTED
CONTROL
INPUT
+ 6 V
VEE
-6 V
VCC
VEE
ENABLE CONTROL
INPUTS
(VCC OR GND)
VEE
VEE
 10 page
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10
VCC = 5 V
16
VHC4316
ENABLE
AND
CONTROL
INPUTS
8
5
6
14
15
TTL
ANALOG
SIGNALS
R*
ANALOG
SIGNALS
HCT
BUFFER
R* = 2 TO 10 k
W
CHANNEL 4
CHANNEL 3
CHANNEL 2
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
12
3
4
CONTROL INPUTS
INPUT
OUTPUT
0.01
mF
LF356 OR
EQUIVALENT
a. Using Pull−Up Resistors
b. Using HCT Buffer
Figure 17. LSTTL/NMOS to HCMOS Interface
Figure 18. Switching a 0−to−12 V Signal Using a
Single Power Supply (GND ≠ 0 V)
Figure 19. 4−Input Multiplexer
Figure 20. Sample/Hold Amplifier
+
-
1 OF 4
SWITCHES
+5 V
16
HC4016A
CONTROL
INPUTS
7
5
6
14
15
LSTTL/
NMOS
ANALOG
SIGNALS
ANALOG
SIGNALS
1 OF 4
SWITCHES
1 OF 4
SWITCHES
1 OF 4
SWITCHES
7
R*
R*
R*
R*
VEE = 0
TO -6 V
9
VEE = 0
TO -6 V
9
12 V
POWER
SUPPLY
R1 = R2
R1
R2
VCC = 12 V
VEE = 0 V
GND = 6 V
12 VPP
ANALOG
INPUT
SIGNAL
C
R3
R4
VCC
VEE
1 OF 4
SWITCHES
ANALOG
OUTPUT
SIGNAL
12 V
0
R1 = R2
R3 = R4




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