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MC74VHC1G14_13 데이터시트(Datasheet) 1 Page - ON Semiconductor

부품명 MC74VHC1G14_13
상세내용  Single Schmitt-Trigger Inverter
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제조사  ONSEMI [ON Semiconductor]
홈페이지  http://www.onsemi.com
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© Semiconductor Components Industries, LLC, 2013
February, 2013 − Rev. 19
1
Publication Order Number:
MC74VHC1G14/D
MC74VHC1G14
Single Schmitt-Trigger
Inverter
The MC74VHC1G14 is a single gate CMOS Schmitt−trigger
inverter fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The MC74VHC1G14 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G14 to be used to interface 5 V circuits to 3 V
circuits.
The MC74VHC1G14 can be used to enhance noise immunity or to
square up slowly changing waveforms.
Features
High Speed: tPD = 4 ns (Typ) at VCC = 5 V
Low Power Dissipation: ICC = 1.0 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 101
These Devices are Pb−Free and are RoHS Compliant
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Figure 1. Pinout (Top View)
VCC
NC
IN A
OUT Y
GND
IN A
OUT Y
Figure 2. Logic Symbol
1
2
3
4
5
1
http://onsemi.com
MARKING
DIAGRAMS
FUNCTION TABLE
L
H
A Input
Y Output
H
L
PIN ASSIGNMENT
1
2
3
GND
NC
IN A
4
5VCC
OUT Y
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
VA
= Device Code
M
= Date Code*
G
= Pb−Free Package
VA M G
G
1
5
VA M G
G
1
5
(Note: Microdot may be in either location)
*Date Code orientation and/or position may
vary depending upon manufacturing location.
TSOP−5 / SOT−23 / SC−59
DT SUFFIX
CASE 483
SC−88A / SOT−353 / SC−70
DF SUFFIX
CASE 419A
 2 page
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MC74VHC1G14
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2
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
−0.5 to )7.0
V
VIN
DC Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to VCC )0.5
V
IIK
DC Input Diode Current
−20
mA
IOK
DC Output Diode Current
$20
mA
IOUT
DC Output Sink Current
$12.5
mA
ICC
DC Supply Current per Supply Pin
$25
mA
TSTG
Storage Temperature Range
*65 to )150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
)150
°C
qJA
Thermal Resistance
SC70−5/SC−88A (Note 1)
TSOP−5
350
230
°C/W
PD
Power Dissipation in Still Air at 85°CSC70−5/SC−88A
TSOP−5
150
200
mW
MSL
Moisture Sensitivity
Level 1
FR
Flammability Rating
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
VESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u200
N/A
V
ILatchup
Latchup Performance
Above VCC and Below GND at 125°C (Note 5)
$500
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2−ounce copper trace with no air flow.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0.0
5.5
V
VOUT
DC Output Voltage
0.0
VCC
V
TA
Operating Temperature Range
*55
)125
°C
tr , tf
Input Rise and Fall Time
VCC = 3.3 V ± 0.3 V
VCC = 5.0 V ± 0.5 V
No Limit
No Limit
ns/V
Device Junction Temperature versus
Time to 0.1% Bond Failures
Junction
Temperature °C
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
1
1
10
100
1000
TIME, YEARS
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Figure 3. Failure Rate vs. Time Junction Temperature
 3 page
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3
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Conditions
VCC
(V)
TA = 25°C
TA ≤ 85°C
−55 ≤ TA ≤ 125°C
Unit
Min
Typ
Max
Min
Max
Min
Max
VT+
Positive Threshold
Voltage
3.0
4.5
5.5
1.85
2.86
3.50
2.0
3.0
3.6
2.20
3.15
3.85
2.20
3.15
3.85
2.20
3.15
3.85
V
VT−
Negative Threshold
Voltage
3.0
4.5
5.5
0.9
1.35
1.65
1.5
2.3
2.9
1.65
2.46
3.05
0.9
1.35
1.65
0.9
1.35
1.65
V
VH
Hysteresis Voltage
3.0
4.5
5.5
0.30
0.40
0.50
0.57
0.67
0.74
1.20
1.40
1.60
0.30
0.40
0.50
1.20
1.40
1.60
0.30
0.40
0.50
1.20
1.40
1.60
V
VOH
Minimum High−Level
Output Voltage
VIN ≤ VT − Min
IOH = −50 mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
V
IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
2.48
3.80
2.34
3.66
V
VOL
Maximum Low−Level
Output Voltage
VIN ≥ VT + Max
IOL = 50 mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IOL = 4 mA
IOL = 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
V
IIN
Maximum Input
Leakage Current
VIN = 5.5 V or GND
0 to
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN = VCC or GND
5.5
1.0
20
40
mA
AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns
Symbol
Parameter
Test Conditions
TA = 25°C
TA ≤ 85°C
−55 ≤ TA ≤ 125°C
Unit
Min
Typ
Max
Min
Max
Min
Max
tPLH,
tPHL
Maximum Propagation
Delay, A to Y
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
7.0
8.5
12.8
16.3
1.0
1.0
15.0
18.5
1.0
1.0
17.0
20.5
ns
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
4.0
5.5
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
11.5
13.5
CIN
Maximum Input
Capacitance
5
10
10
10
pF
CPD
Power Dissipation Capacitance (Note 6)
Typical @ 25°C, VCC = 5.0 V
pF
7.0
6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC. CPD is used to determine the no−load dynamic
power consumption; PD = CPD  VCC2  fin + ICC  VCC.
 4 page
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4
VCC
GND
50%
50% VCC
A or B
Y
tPHL
tPLH
Figure 4. Switching Waveforms
Figure 5. Test Circuit
*Includes all probe and jig capacitance.
A 1−MHz square input wave is recommended for propagation delay tests.
CL*
INPUT
OUTPUT
ORDERING INFORMATION
Device
Package
Shipping
MC74VHC1G14DFT1G
SC−88A/SOT−353
(Pb−Free)
3000/Tape & Reel
NLVVHC1G14DFT1G*
MC74VHC1G14DFT2G
NLVVHC1G14DFT2G*
MC74VHC1G14DTT1G
SOT−23/TSOP−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
 5 page
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MC74VHC1G14
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5
PACKAGE DIMENSIONS
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419A−01 OBSOLETE. NEW STANDARD
419A−02.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
DIM
A
MIN
MAX
MIN
MAX
MILLIMETERS
1.80
2.20
0.071
0.087
INCHES
B
1.15
1.35
0.045
0.053
C
0.80
1.10
0.031
0.043
D
0.10
0.30
0.004
0.012
G
0.65 BSC
0.026 BSC
H
---
0.10
---
0.004
J
0.10
0.25
0.004
0.010
K
0.10
0.30
0.004
0.012
N
0.20 REF
0.008 REF
S
2.00
2.20
0.079
0.087
B
0.2 (0.008) MM
12
3
4
5
A
G
S
D 5 PL
H
C
N
J
K
−B−
SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE K
 6 page
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6
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
DIM
MIN
MAX
MILLIMETERS
A
3.00 BSC
B
1.50 BSC
C
0.90
1.10
D
0.25
0.50
G
0.95 BSC
H
0.01
0.10
J
0.10
0.26
K
0.20
0.60
L
1.25
1.55
M
0
10
S
2.50
3.00
12
3
54
S
A
G
L
B
D
H
C
J
__
0.7
0.028
1.0
0.039
mm
inches
SCALE 10:1
0.95
0.037
2.4
0.094
1.9
0.074
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.20
5X
C AB
T
0.10
2X
2X
T
0.20
NOTE 5
T
SEATING
PLANE
0.05
K
M
DETAIL Z
DETAIL Z
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
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PUBLICATION ORDERING INFORMATION
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
MC74VHC1G14/D
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