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MRF89XA 데이터시트(PDF) 84 Page - Microchip Technology |
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MRF89XA 데이터시트(HTML) 84 Page - Microchip Technology |
84 / 140 page MRF89XA DS70000622D-page 84 Preliminary 2010-2017 Microchip Technology Inc. 3.11.1 TX PROCESSING In TX mode, the packet handler dynamically builds the packet by performing the following operations on the payload available in the FIFO: • Adding a programmable number of preamble bytes • Adding a programmable Sync Word • Optionally calculating CRC over complete pay- load field (optional length byte plus optional address byte plus message) and appending the 2 bytes checksum • Optional support for DC-free encoding of the data (Manchester or Whitening) Only the payload (including optional address and length fields) should be provided by the user in the FIFO. Assuming that the device is in TX mode, and then depending on the setting of the IRQ0TXST bit (FTPRI- REG<4>), packet transmission (starting with pro- grammed preamble) starts either after the first byte is written into the FIFO (IRQ0TXST = 1) or after the num- ber of bytes written reaches the user-defined threshold (IRQ0TXST = 0). The FIFO can be fully or partially filled in Standby mode through the FRWAXS bit (FCRCREG<6>). In this case, the start condition is only checked when entering TX mode. At the end of the transmission (TXDONE = 1), the user must exit TX mode if required (for example, back to Standby mode). While in TX mode, before and after packet transmis- sion (not enough bytes or TXDONE), additional pream- ble bytes are sent to the modulator. When the start condition is met, the current additional preamble byte is completely sent before the transmission of the next packet (that is, programmed preamble) is started. 3.11.2 RX PROCESSING In RX mode the packet handler extracts the user payload to the FIFO by performing the following operations: • Receiving the preamble and stripping off the preamble • Detecting the Sync Word and stripping off the Sync Word • Optional DC-free decoding of data • Optionally checking the address byte • Optionally checking CRC and reflecting the result on the STSCRCEN bit (PKTREG<0>) and CRCOK from IRQ source (for more information, refer to Register 2-14). Only the payload (including optional address and length fields) is made available in the FIFO. PLREADY and CRCOK interrupts (the latter only if CRC is enabled) can be generated to indicate the end of the packet reception (for more information, refer to Register 2-14). By default, if the CRC check is enabled and fails for the current packet, the FIFO is automatically cleared and neither of the two interrupts is generated and a new packet reception is started. This autoclear function can be disabled via the ACFCRC bit (FCRCREG<7>) and, in this case, even if CRC fails, the FIFO is not cleared and only the PLREADY IRQ source is issued. Once fully received, the payload can also be fully or partially retrieved in Standby mode from the FRWAXS bit. At the end of the reception, although the FIFO auto- matically stops being filled, it still depends on the user to explicitly exit RX mode if required (for example, go to Standby mode to get payload). The FIFO must be empty for a new packet reception to start. 3.11.3 PACKET FILTERING The MRF89XA packet handler offers several mecha- nisms for packet filtering ensuring that only useful packets are made available to the host microcontroller, significantly reducing system power consumption and software complexity. 3.11.3.1 Sync Word-Based Sync Word filtering or recognition is enabled in Packet mode. It is used for identifying the start of the payload and also for network identification. As described earlier, the Sync Word recognition block is configured (with size, error tolerance, value) from the SYNCREN, SYN- CWSZ, SYNCTEN, SYNCV31-0 bits in the SYNCREG, SYNCV31REG, SYNCV23REG, SYNCV15REG, and SYNCV07REG Configuration registers. This informa- tion is used for appending Sync Word in TX and filtering packets in RX. Every received packet that does not start with this locally configured Sync Word is automatically dis- carded, and no interrupt is generated. When the Sync Word is detected, payload reception automatically starts and the Sync IRQ source is issued. 3.11.3.2 Length-Based In variable length Packet mode, the PLDPLEN<6:0> bits (PLOADREG<6:0>) must be programmed with the maximum length permitted. If the received length byte is smaller than this maximum, the packet is accepted and processed; otherwise, it is discarded. To disable this function, the user should set the value of the PLDPLEN<6:0> bits to the value of the FIFO size selected. Note: The received length byte, as part of the payload, is not stripped off the packet and is made available in the FIFO. |
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