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CAT24WC257PTE13 데이터시트(PDF) 3 Page - Catalyst Semiconductor |
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CAT24WC257PTE13 데이터시트(HTML) 3 Page - Catalyst Semiconductor |
3 / 10 page CAT24WC257 3 Doc. No. 1030, Rev. E Power-Up Timing (2)(3) Symbol Parameter Min Typ Max Units tPUR Power-Up to Read Operation 1 ms tPUW Power-Up to Write Operation 1 ms Note: (1) AC measurement conditions: RL (connects to VCC): 0.3VCC to 0.7 VCC Input rise and fall times: < 50ns Input and output timeing reference voltages: 0.5 VCC (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address. A.C. CHARACTERISTICS VCC = +1.8V to +6V, unless otherwise specified Output Load is 1 TTL Gate and 100pF Read & Write Cycle Limits Symbol Parameter VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V Min Max Min Max Min Max Units FSCL Clock Frequency 100 400 1000 kHz tAA SCL Low to SDA Data Out 0.1 3.5 0.05 0.9 0.05 0.55 µs and ACK Out tBUF(1) Time the Bus Must be Free Before 4.7 1.2 0.5 µs a New Transmission Can Start tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tLOW Clock Low Period 4.7 1.2 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tSU:STA Start Condition Setup Time 4.0 0.6 0.25 µs (for a Repeated Start Condition) tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 100 100 100 ns tR(1) SDA and SCL Rise Time 1.0 0.3 0.3 µs tF(1) SDA and SCL Fall Time 300 300 100 ns tSU:STO Stop Condition Setup Time 4.7 0.6 0.25 µs tDH Data Out Hold Time 100 50 50 ns tWR Write Cycle Time 10 10 10 ms |
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