전자부품 데이터시트 검색엔진 |
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TDS7054 데이터시트(PDF) 6 Page - List of Unclassifed Manufacturers |
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TDS7054 데이터시트(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 12 page Oscilloscopes • www.tektronix.com/tds7000B 6 Digital Phosphor Oscilloscopes TDS7000B Series Trigger Modes Edge – Positive and/or negative slope on any channel or front panel auxiliary input. Coupling includes DC, AC, noise reject, HF reject and LF reject. Glitch – Trigger on or reject glitches of positive, negative or either polarity. Minimum glitch width is 1.0 ns with 200 ps resolution (TDS7104/TDS7054). Minimum glitch width is 170 ps (TDS7704B) or 225 ps (all other B models) with rearm time of 250 ps (B models). Width – Trigger on width of positive or negative pulse (down to 170 ps on B models) either within or out of selectable time limits – 1 ns (TDS7104/ TDS7054) or 340 ps (B models) to 1 s. Runt – Trigger on a pulse that crosses one threshold but fails to cross a second threshold before crossing the first again. Optional time qualification. Timeout – Trigger on an event which remains high, low or either, for a specified time period, selectable from 1 ns (TDS7104/TDS7054) or 340 ps (B models) to 1 s with 200 ps (TDS7104/TDS7054) or 100 ps (B models). Transition – Trigger on pulse edge rates that are faster or slower than specified. Slope may be positive, negative or either. Setup/Hold – Trigger on violations of both setup time and hold time between clock and data present on any two input channels. Pattern – Trigger when pattern goes false or stays true for specified period of time. Pattern (AND, OR, NAND, NOR) specified for four input channels defined as HIGH, LOW or Don’t Care. State – Any logical pattern of channels (1, 2, 3) clocked by edge on channel 4. Trigger on rising or falling clock edge. Window – Trigger on an event that enters or exits a window defined by two user-adjustable thresholds. Event can be time or logic qualified (B models only). Logic Qualified Trigger applicable to Glitch, Width, Runt, Timeout, Transition, Setup/Hold, Window triggers – Trigger on the specified event only if the logic state defined with the remaining unused chan- nels occurs (B models only). Trigger Delay by Time – 16 ns (5 ns for B models) to 250 seconds. Trigger Delay by Events – 1 to 10,000,000 Events. Clock Recovery System (Option SM, ST) TDS7154B/TDS7254B/TDS7404B/TDS7704B Clock Recovery Phase Locked Loop Bandwidth Fbaud/1600 typical Tracking/Acquisition Range ±2% of requested baud Clock Recovery Jitter (typical) 0.25% period +5 ps RMS for PRBS data pattern or 4 psRMS for repeating “011” data patterns Input Sensitivity for Clock Recovery 1 division peak-to-peak displayed signal Input Data Rates 1.5 Mbaud to 3.125 Gbaud |
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