전자부품 데이터시트 검색엔진 |
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SLG46200 데이터시트(PDF) 65 Page - Dialog Semiconductor |
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SLG46200 데이터시트(HTML) 65 Page - Dialog Semiconductor |
65 / 69 page 000-0046200-124 Page 60 of 64 SLG46200 reg<355:354> Internal OSC current select 00: 0.5 μA 01: 1 μA 10: 2 μA 11: 10 μA reg<356> Internal OSC VREF select: 0: 1.5V 1: 0.5V reg<357> PGA gain to ACMP0 input enable 0: Disable 1: Enable reg<361:358> ACMP0 VREF select: 0000: 50mV 1000: 600mV 0001: 100mV 1001: 700mV 0010: 150mV 1010: 800mV 0011: 200mV 1011: 900mV 0100: 250mV 1100: 1100mV 0101: 300mV 1101: 1300mV 0110: 400mV 1110: 1500mV 0111: 500mV 1111: Ext_Vref (PIN 8) reg<362> ADC's DAC VREF feedback select 0: Normal 1: 0.5x gain reg<366:363> ACMP1 VREF select: 0000: 50mV 1000: 600mV 0001: 100mV 1001: 700mV 0010: 150mV 1010: 800mV 0011: 200mV 1011: 900mV 0100: 250mV 1100: 1100mV 0101: 300mV 1101: 1300mV 0110: 400mV 1110: 1500mV 0111: 500mV 1111: Ext_Vref (PIN 8) reg<367> VREF output buffer enable 0: VREF output through buffer 1: VREFoutput not through buffer reg<368> VREF output source select 0: ACMP0's VREF 1: VDD/2 reg<369> ACMP0 hysteresis enable 0: Disable 1: Enable reg<370> ACMP1 hysteresis enable 0: Disable 1: Enable reg<371> ADC pseudo diff input enable under diff mode 0: Disable 1: Enable reg<373:372> PIN 3 digital out source selection 00/01: From connection matrix output <12> 10: S2P serial output data 11: ADC serial output data reg<374> S2P in/out mode control 0: S2P serial input mode 1: P2S serial output mode reg<382:375> Digital comparator negative port input (in2 of DCMP0 and in3 of DCMP1) reg<390:383> Digital comparator negative port input (in3 of DCMP0 and in4 of DCMP1) reg<398:391> Digital comparator negative port input (in4 of DCMP0 and in2 of DCMP1) Bit Address Definition |
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