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SLG46400 데이터시트(PDF) 56 Page - Dialog Semiconductor

부품명 SLG46400
상세설명  GreenPAK 2TM Rev.B Programmable Mixed Signal Array
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SLG46400
14.0 Programmable Delay (PDLY)
The SLG46400 has a programmable time delay logic cell available that can generate a maximum delay of 200ns. The program-
mable time delay cell has four delay cells with a typical value of 20ns per cell (based on a VDD of 3.3V). The delay cells are tied
in series where the output of each delay cell goes to the next delay cell and to a 4-input mux that is controlled by reg<537:536>.
14.1 Programmable Delay Functional Diagram
14.2 VDD vs. Typical Time Delay
14.3 Programmable Delay Register Settings
Figure 28. Programmable Delay Functional Diagram
Table 21. VDD vs. Typical Time Delay per 1 Cell.
VDD (V)
Typical Time Delay (ns)
5.0V
10ns
3.3V
20ns
1.8V
50ns
Table 22. Programmable Delay Register Settings
Signal Name
Signal Function
Register Bit
Address
Register Definition
PDLY_sel
PDLY value section
<537:536>
00: 1 delay cell active
01: 2 delay cells active
10: 3 delay cells active
11: 4 delay cells active
Delay
20ns
Delay
20ns
Delay
20ns
Delay
20ns
From Connection
Matrix output <6>
01
00
11
10
reg<537:536>
To Connection
Matrix input <47>
OUT
IN


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