MPEG-4 Video Decoder LSI

Preliminary

TC35274

TOSHIBA Confidential

2000-4-27

3/13

Version 0.90

1. Functional Specifications

1.1 MPEG-4 Video Decoder

ISO MPEG-4 IS SP@L1 decoding is executed with QCIF (176x144 pixels) at 15 frames/sec.

YCbCr 4:2:2 8bit digital image data output to a LCD via an external LCD controller.

Size conversion and de-blocking filter operatation.

16-bit parallel host interface.

1.2 System Configurations

Fig. 1 illustrates a block diagram of TC35274.

z Before starting operation, an external host CPU downloads a firmware into an embedded

DRAM via a host interface.

z Encoded video bitstream are transferred from a host CPU via a host interface, and stored

into the embedded DRAM. Then, an MPEG-4 video core decodes the bitstream.

z The decoded pictures output to an external LCD controller via an LCD I/F.

Fig. 1 Block diagram of TC35274

* In order to run this LSI as an MEPG-4 video decoder LSI, Specified firmware programs have to be

obtained in advance.

4Mb Embedded DRAM

Arbiter + DRAM Controller

LCD

I/F

Host

I/F

DMAController

HW

RISC

HW

MPEG-4 Video

LCDC

Host

CPU