ADF4154

Rev. 0 | Page 10 of 20

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4154 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 (see Table 9).

Figure 21 shows the MUXOUT section in block diagram form.

The N-channel, open-drain, analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When lock has been detected, the lock detect is high with

narrow low-going pulses.

R-DIVIDER OUTPUT

N-DIVIDER OUTPUT

ANALOG LOCK DETECT

DGND

CONTROL

MUX

MUXOUT

LOGIC LOW

FAST-LOCK CONTROL

THREE-STATE OUTPUT

DIGITAL LOCK DETECT

LOGIC HIGH

Figure 21. MUXOUT Schematic

INPUT SHIFT REGISTERS

The ADF4154 digital section includes a 4-bit RF R counter, a

9-bit RF N counter, a 12-bit FRAC counter, and a 12-bit

modulus counter. Data is clocked into the 24-bit shift register

on each rising edge of CLK. The data is clocked in MSB first.

Data is transferred from the shift register to one of four latches

on the rising edge of LE. The destination latch is determined by

the state of the two control bits (C2 and C1) in the shift register.

These are the 2 LSBs, DB1, and DB0, as shown in Figure 2. The

truth table for these bits is shown in Table 5. Table 6 shows a

summary of how the latches are programmed.

PROGRAM MODES

Table 5 through Table 10 show how to set up the program

modes in the ADF4154.

The ADF4154 programmable modulus is double-buffered. This

means that two events have to occur before the part uses a new

modulus value. First, the new modulus value is latched into the

device by writing to the R-divider register. Second, a new write

must be performed on the N-divider register. Therefore, when-

ever the modulus value is updated, the N-divider register must

then be written to so that the modulus value is loaded correctly.

Table 5. C2 and C1 Truth Table

Control Bits

C2

C1

Data Latch

0

0

N-divider register

0

1

R-divider register

1

0

Control register

1

1

Noise and spur register