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CY7C1441KV33 데이터시트(PDF) 10 Page - Cypress Semiconductor

부품명 CY7C1441KV33
상세설명  36-Mbit (1M36/2M18) Flow-Through SRAM (With ECC)
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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CY7C1441KV33
CY7C1443KV33
CY7C1441KVE33
Document Number: 001-66677 Rev. *I
Page 10 of 32
Truth Table
The truth table for CY7C1441KV33/CY7C1443KV33/CY7C1441KVE33 is as follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselected Cycle, Power down
None
H
X
X
L
X
L
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
L
L
X
L
L
X
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
L
X
H
L
L
X
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
L
L
X
L
H
L
X
X
X
L–H
Tristate
Deselected Cycle, Power down
None
X
X
H
L
H
L
X
X
X
L–H
Tristate
Sleep Mode, Power down
None
X
X
X
H
X
X
X
X
X
X
Tristate
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H
Tristate
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H
Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tristate
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tristate
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tristate
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tristate
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
1. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care
for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).


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