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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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CY7C1444KV33 데이터시트(PDF) 7 Page - Cypress Semiconductor |
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CY7C1444KV33 데이터시트(HTML) 7 Page - Cypress Semiconductor |
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7 / 22 page  CY7C1444KV33 CY7C1445KV33 Document Number: 001-66678 Rev. *G Page 7 of 22 Because the CY7C1444KV33/CY7C1445KV33 are common I/O devices, the output enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will tristate the output drivers. As a safety precaution, DQX are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1444KV33/CY7C1445KV33 provide a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 Second Address A1: A0 Third Address A1: A0 Fourth Address A1: A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max Unit IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 75 mA tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns |
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