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HCF4052M013TR 데이터시트(PDF) 6 Page - STMicroelectronics |
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HCF4052M013TR 데이터시트(HTML) 6 Page - STMicroelectronics |
6 / 11 page HCF4052B 6/11 TYPICAL BIAS VOLTAGES The ADDRESS (digtal-control inputs) and INHIBIT logic levels are : "0"=VSS and "1"=VDD. The analog signal (through the TG) may swing from VEE to VDD TYPICAL APPLICATIONS (TYPICAL TIME-DIVISION APPLICATION) SPECIAL CONSIDERATIONS Control of analog signals up to 20V peak to peak can be achieved by digital signal amplitudes of 4.5 to 20V (if VDD -VSS =3V, aVDD -VEE of up to 13V can be controlled; for VDD -VEE level differences above 13V, a VDD -VSS of at least 4.5V is required. For example, if VDD =+5, VSS =0, and VEE = -13.5, analog signals from -13.5V to 4.5V can be controlled by digital inputs of 0 to 4.5V. In certain applications, the external load resistor current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0,8V (calculated from RON values shown in DC SPECIFICATIONS). No VDD current will flow through RL if the switch current flows into leads 3 and 13. |
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