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S29GL512N 데이터시트(PDF) 81 Page - Cypress Semiconductor

부품명 S29GL512N
상세설명  512, 256, 128 Mbit, 3 V, Page Flash Featuring 110 nm MirrorBit
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

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Document Number: 002-01522 Rev. *B
Page 81 of 92
S29GL512N
S29GL256N
S29GL128N
Notes
1. VIO < VCC + 200 mV.
2. VIO and VCC ramp must be in sync during power up. If RESET# is not stable for 35 µs, the following conditions may occur: the device does not permit any read and
write operations, valid read operations return FFh, and a hardware reset is required.
3. Maximum VCC power up current is 20 mA (RESET# =VIL).
Figure 19.2
Power-On Reset Timings
Power-Up Sequence Timings
Parameter
Description
Speed
Unit
tVCS
Reset Low Time from Rising Edge of VCC (or last Reset pulse) to Rising
Edge of RESET#
Min
35
µs
tVIOS
Reset Low Time from Rising Edge of VIO (or last Reset pulse) to Rising
Edge of RESET#
Min
35
µs
tRH
Reset High Time Before Read
Max
200
ns
CE#
RESET#
tRH
V
Vcc_min
V
Vio_min
tVCS
tVIOS
CC
IO


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