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74AC11109DR 데이터시트(PDF) 4 Page - Texas Instruments

부품명 74AC11109DR
상세설명  DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET
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74AC11109DR 데이터시트(HTML) 4 Page - Texas Instruments

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54AC11109, 74AC11109
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS450 – MARCH 1987 – REVISED APRIL 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
2–4
timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1)
TA = 25°C
54AC11109
74AC11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
70
0
70
0
70
MHz
t
Pulse duration
PRE or CLR low
5
5
5
ns
tw
Pulse duration
CLK low or CLK high
7.2
7.2
7.2
ns
t
Setup time before CLK
Data high or low
5.5
5.5
5.5
ns
tsu
Setup time before CLK
PRE or CLR inactive
2.5
2.5
2.5
ns
th
Hold time after CLK
0
0
0
ns
timing requirements, VCC = 5 V ± 0.5 V (see Figure 1)
TA = 25°C
54AC11109
74AC11109
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fclock
Clock frequency
0
100
0
100
0
100
MHz
t
Pulse duration
PRE or CLR low
4
4
4
ns
tw
Pulse duration
CLK low or CLK high
5
5
5
ns
t
Setup time before CLK
Data high or low
4.5
4.5
2.5
ns
tsu
Setup time, before CLK
PRE or CLR inactive
2
2
2
ns
th
Hold time, after CLK
0
0
0
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C
54AC11109
74AC11109
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
70
100
70
70
MHz
tPLH
PRE or CLR
QorQ
1.5
6.5
9
1.5
10.5
1.5
9.9
ns
tPHL
PRE or CLR
Q or Q
1.5
8
12.6
1.5
14.4
1.5
13.7
ns
tPLH
CLK
QorQ
1.5
8
11.4
1.5
13.5
1.5
12.7
ns
tPHL
CLK
Q or Q
1.5
7.5
10.5
1.5
12.7
1.5
11.8
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
TA = 25°C
54AC11109
74AC11109
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
100
125
100
100
MHz
tPLH
PRE or CLR
QorQ
1.5
4.5
6.5
1.5
7.6
1.5
7.1
ns
tPHL
PRE or CLR
Q or Q
1.5
5
8.6
1.5
10.2
1.5
9.6
ns
tPLH
CLK
QorQ
1.5
5.5
7.9
1.5
9.4
1.5
8.8
ns
tPHL
CLK
Q or Q
1.5
5
7.3
1.5
8.6
1.5
8.1
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance per gate
CL = 50 pF,
f = 1 MHz
32
pF


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