74AC11648

OCTAL BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCAS114 – MARCH 1990 – REVISED APRIL 1993

POST OFFICE BOX 655303

2–3

FUNCTION TABLE

INPUTS

DATA I/O

OPERATION OR FUNCTION

OE

DIR

CLKAB

CLKBA

SAB

SBA

A1 THRU A8

B1 THRU B8

OPERATION OR FUNCTION

X

X

↑

X

X

X

Input

Unspecified†

Store A, B unspecified†

X

XX

↑

X

X

Unspecified†

Input

Store B, A unspecified†

H

X

↑

↑

X

X

Input

Input

Store A and B data

H

X

L

L

X

X

Input disabled

Input disabled

Isolation, hold storage

L

L

X

X

X

L

Output

Input

Real-time B data to A bus

L

L

X

L

X

H

Output

Input

Stored B data to A bus

L

H

X

X

L

X

Input

Output

Real-time A data to B bus

L

H

L

X

H

X

Input

Output

Stored A data to B bus

† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;

i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.

OE

G3

1

3 EN2 [AB]

G5

15

SBA

A1

2

B1

20

4D

3 EN1 [BA]

14

DIR

16

CLKBA

28

CLKAB

G7

27

SAB

5

7

7

5

1

1

6D

≥1

≥1

1

2

C6

B2

25

A2

3

B3

24

A3

4

B4

23

A4

5

B5

20

A5

10

B6

19

A6

11

B7

18

A7

12

B8

17

A8

13

C4

‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.