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ADC08D500EVAL 데이터시트(PDF) 11 Page - Analog Devices

부품명 ADC08D500EVAL
상세설명  High Performance, Low Power, Dual 8-Bit, 500 MSPS A/D Converter
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Converter Electrical Characteristics (Continued)
The following specifications apply after calibration for V
A =VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mV
P-P,CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 500 MHz at 0.5VP-P with 50% duty cycle, VBG =
Floating, Non-Extended Control Mode, SDR Mode, R
EXT = 3300
±0.1%, Analog Signal Source Impedance = 100Ω Differen-
tial. Boldface limits apply for T
A =TMIN to TMAX. All other limits TA = 25˚C, unless otherwise noted. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
AC ELECTRICAL CHARACTERISTICS
DCLK Duty Cycle
(Note 12)
50
45
55
% (min)
% (max)
t
RS
Reset Setup Time
(Note 12)
150
ps
t
RH
Reset Hold Time
(Note 12)
250
ps
t
SD
Syncronizing Edge to DCLK Output
Delay
f
CLKIN = 500 MHz
f
CLKIN = 200 MHz
3.53
3.85
ns
t
RPW
Reset Pulse Width
(Note 11)
4
Clock Cycles
(min)
t
LHT
Differential Low to High Transition
Time
10% to 90%, C
L = 2.5 pF
250
ps
t
HLT
Differential High to Low Transition
Time
10% to 90%, C
L = 2.5 pF
250
ps
t
OSK
DCLK to Data Output Skew
50% of DCLK transition to 50% of
Data transition, SDR Mode
and DDR Mode, 0˚ DCLK (Note 12)
±50
ps (max)
t
SU
Data to DCLK Set-Up Time
DDR Mode, 90˚ DCLK (Note 12)
2
ns
t
H
DCLK to Data Hold Time
DDR Mode, 90˚ DCLK (Note 12)
2
ns
t
AD
Sampling (Aperture) Delay
Input CLK+ Fall to Acquisition of
Data
1.3
ns
t
AJ
Aperture Jitter
0.4
ps rms
t
OD
Input Clock to Data Output Delay
(in addition to Pipeline Delay)
50% of Input Clock transition to
50% of Data transition
3.1
ns
Pipeline Delay (Latency)
(Notes 11, 14)
DI Outputs
13
Clock Cycles
DId Outputs
14
DQ Outputs
Normal Mode
13
DES Mode
13.5
DQd Outputs
Normal Mode
14
DES Mode
14.5
Over Range Recovery Time
Differential V
IN step from ±1.2V to
0V to get accurate conversion
1
Input Clock
Cycle
t
WU
PD low to Rated Accuracy
Conversion (Wake-Up Time)
500
ns
f
SCLK
Serial Clock Frequency
(Note 12)
100
MHz
t
SSU
Data to Serial Clock Setup Time
(Note 12)
2.5
ns (min)
t
SH
Data to Serial Clock Hold Time
(Note 12)
1
ns (min)
Serial Clock Low Time
4
ns (min)
Serial Clock High Time
4
ns (min)
t
CAL
Calibration Cycle Time
1.4 x 10
5
Clock Cycles
t
CAL_L
CAL Pin Low Time
See Figure 9 (Note 11)
80
Clock Cycles
(min)
t
CAL_H
CAL Pin High Time
See Figure 9 (Note 11)
80
Clock Cycles
(min)
t
CalDly
Calibration delay determined by pin
127
See Section 1.1.1, Figure 9, (Note
15)
2
25
Clock Cycles
(min)
www.national.com
11


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