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CM3121 데이터시트(PDF) 1 Page - California Micro Devices Corp

부품명 CM3121
상세설명  Dual Linear Voltage Regulator for DDR-I and DDR-II Memory
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제조업체  CALMIRCO [California Micro Devices Corp]
홈페이지  http://www.calmicro.com
Logo CALMIRCO - California Micro Devices Corp

CM3121 데이터시트(HTML) 1 Page - California Micro Devices Corp

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© 2004 California Micro Devices Corp. All rights reserved.
11/12/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
CM3121
PRELIMINARY
Dual Linear Voltage Regulator for DDR-I and DDR-II Memory
Features
Fully integrated power solution for DDR memory
ICs
Ideal for DDR-I (2.5VDDQ) and DDR-II (1.8VDDQ)
Lowest system cost and smallest footprint with just
two external output capacitors
Two linear regulators:
- VDDQ regulator with a maximum output current
of 1.5A shared by DRAM and VTT regulator
- source-sink VTT regulator with maximum out-
put current of 0.5A (DDR-I) or 0.3A (DDR-II)
Fault output indicates overcurrent condition in
either regulator, under voltage lock-out and over-
temperature condition
Reverse current protection if host is powered off
PSOP-8 package with integrated heat spreader
Lead-free versions available
Applications
DDR-I and DDR-II memory power for:
Set Top Boxes, DVD Players, Games
Digital TVs, Flat Panel Displays
Printers, Digital Projectors
Embedded systems
Communications systems
Product Description
The CM3121 provides an integrated power solution for
DDR-I and DDR-II memory systems in consumer electron-
ics applications. The CM3121 is ideal for a 2.8V to 3.6V
supply for DDR-I memory and 2.2V to 2.8V for DDR-II mem-
ory. The CM3121 features two independent linear regula-
tors for VDDQ and VTT supply regulation. The default
voltage for VDDQ is 2.5V. The VDDQ regulator SENSE pin
allows for setting VDDQ in the 2.2V to 2.8V range, or DDR-II
memories from 1.7V to 1.9V. The VTT regulator output is
always half the VDDQ voltage, derived internally. A capacitor
should be connected to each of the two outputs.
When EN_DDR is set high, the two DDR regulators are dis-
abled to minimize overall system power dissipation such as
when memory is in standby.
The FAULT pin goes low whenever either of the two regula-
tors goes into current limit mode, the input voltage drops too
far or if overtemp occurs.
The CM3121 is available in a PSOP-8 package that has
excellent thermal dissipation. It is available with optional
lead-free finishing.
.
Typical Application Circuit
Circuit Schematic
VREF
R
R
FAULT
VTT=1.25V
VDDQ = 2.5V
VDDQ
REGULATOR
VTT
REGULATOR
EN_DDR
VCC
GND
CDDQ
DDR
MEMORY
CPU
CORE
+ I/O
CCC
CTT
Enable DDR
Memory #
2.8V to 3.3V
SENSE VTT
VTT
SENSE VTT
VDDQ
SENSE
VDDQ
CURRENT LIMIT
OVERTEMP
LOW INPUT
VREF
R
R
FAULT
VDDQ
REGULATOR
VTT
REGULATOR
GND
SENSE VTT
VTT
SENSE VTT
VDDQ
SENSE
VDDQ
CURRENT LIMIT
OVERTEMP
LOW INPUT
SENSE_VTT
VTT
SENSE_ VDDQ
VDDQ
VCC
EN_DDR


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