LTM4661

12

4661f

For more information www.linear.com/LTM4661

respectively.Inpractice,powerlossisthermallydissipated

in both directions away from the package—granted, in

the absence of a heat sink and airflow, a majority of the

heat flow is into the board.

Within a SIP (system-in-package) module, be aware there

are multiple power devices and components dissipating

power, with a consequence that the thermal resistances

relative to different junctions of components or die are not

exactly linear with respect to total package power loss. To

reconcile this complication without sacrificing modeling

simplicity—but also, not ignoring practical realities—an

approach has been taken using FEA software modeling

along with laboratory testing in a controlled-environment

chamber to reasonably define and correlate the thermal

resistance values supplied in this data sheet: (1) Initially,

FEA software is used to accurately build the mechanical

geometry of the µModule and the specified PCB with all

of the correct material coefficients along with accurate

power loss source definitions; (2) this model simulates

a software-defined JEDEC environment consistent with

JESD51-9 to predict power loss heat flow and temperature

readingsatdifferentinterfacesthatenablethecalculationof

theJEDEC-definedthermalresistancevalues;(3)themodel

and FEA software is used to evaluate the µModule with

heat sink and airflow; (4) having solved for and analyzed

these thermal resistance values and simulated various

operating conditions in the software model, a thorough

laboratory evaluation replicates the simulated conditions

with thermocouples within a controlled-environment

chamber while operating the device at the same power

loss as that which was simulated. An outcome of this

process and due diligence yields a set of derating curves

provided in other sections of this data sheet. After these

laboratory tests have been performed and correlated to

togethertocorrelatequitewellwiththeµModulemodelwith

no airflow or heat sinking in a properly defined chamber.

approximately 100% of power loss flows from the junc-

tion through the board into ambient with no airflow or top

mounted heat sink.

The 5V, 8V, 12V and 15V output power loss curves in

Figures 4 to 7 can be used in coordination with the load

current derating curves in Figures 8 to 14 for calculating

with various heat sinking and airflow conditions. The

power loss curves are taken at room temperature and

are increased with multiplicative factors according to the

ambient temperature. These approximate factors is 1.4

assuming the junction temperature at 110°C. The output

voltages are chosen to include the lower and higher out-

put voltage ranges for correlating the thermal resistance.

Thermal models are derived from several temperature

measurementsinacontrolledtemperaturechamberalong

withthermalmodelinganalysis.Thejunctiontemperatures

are monitored while ambient temperature is increased

with and without airflow. The power loss increase with

ambient temperature change is factored into the derating

APPLICATIONS INFORMATION

Figure 3. Graphical Representation of JESD51-12 Thermal Coefficients

4661 F03

µMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

AMBIENT

CASE (BOTTOM)-TO-BOARD

RESISTANCE