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NBSG16BAEVB 데이터시트(PDF) 3 Page - ON Semiconductor |
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NBSG16BAEVB 데이터시트(HTML) 3 Page - ON Semiconductor |
3 / 10 page NBSG16 http://onsemi.com 3 50 W 50 W VTD D D VTD VMM Q Q VBB VEE VCC Figure 3. Logic Diagram 75 k W 75 k W 36.5 KW Table 2. Interfacing Options INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD together AC-COUPLED Bias VTD and VTD Inputs within (VIHCMR) Common Mode Range RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL The external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. |
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