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SI4133G-X2 데이터시트(PDF) 9 Page - List of Unclassifed Manufacturers |
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SI4133G-X2 데이터시트(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 32 page Si4133G-X2 Rev. 0.9 9 Figure 4. Hardware Power Management Timing Diagram Figure 5. Software Power Management Timing Diagram RF1 Reference Spurs Offset = 200 kHz — –70 — dBc Offset = 400 kHz — –75 — dBc Offset = 600 kHz — –80 — dBc R F2 Reference Spurs Offset = 200 kHz — –75 — dBc Offset = 400 kHz — –80 — dBc Offset = 600 kHz — –80 — dBc Power Up Request to Synthesizer Ready Time, RF1, RF2, IF2 t pup Figures 4, 5 — 140 — µs Power Down Request to Synthesizer Off Time3 t pdn Figures 4, 5 — — 100 ns Table 5. RF and IF Synthesizer Characteristics (Continued) (VDD = 2.7 to 3.6 V, TA = –20 to 85°C) Parameter1 Symbol Test Condition Min Typ Max Unit Notes: 1. RF1 = 1.55 GHz, RF2 = 1.4 GHz, IF = 1080 MHz., RFPWR=0 for all parameters unless otherwise noted. 2. From power up request (PWDNB ↑ or SENB↑ during a write of 1 to bits PDAB, PDIB, and PDRB in register 2) to RF and IF synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120 µs. 3. From power down request (PWDNB ↓, or SENB↑ during a write of 0 to bits PDAB, PDIB, and PDRB in register 2) to supply current equal to IPWDN. |
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