전자부품 데이터시트 검색엔진 |
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CD74HCT356E 데이터시트(PDF) 8 Page - Texas Instruments |
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CD74HCT356E 데이터시트(HTML) 8 Page - Texas Instruments |
8 / 8 page 8 FIGURE 4. SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION-DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS FIGURE 5. 3-STATE PROPAGATION-DELAY WAVEFORM NOTE: Open-drain waveforms tPLZ and tPZL are the same as those for 3-state shown on the left. The test circuit is Output RL =1kΩ to VCC, CL = 50pF. FIGURE 6. 3-STATE PROPAGATION-DELAY TEST CIRCUIT Test Circuits and Waveforms (Continued) trCL tfCL GND 3V GND 3V 1.3V 2.7V 0.3V GND CLOCK INPUT DATA INPUT OUTPUT SET, RESET OR PRESET 3V 1.3V 1.3V 1.3V 90% 10% 1.3V 90% tREM tPLH tSU(H) tTLH tTHL tH(L) tPHL IC CL 50pF tSU(L) 1.3V tH(H) 1.3V 0.3 2.7 GND 3V 10% 90% 1.3V 1.3V OUTPUT DISABLE OUTPUT LOW TO OFF OUTPUT HIGH TO OFF OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED tr 6ns tPZH tPHZ tPZL tPLZ 6ns tf 1.3 IC WITH OUTPUT OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH RL = 1kΩ CL 50pF 3-STATE OUTPUT CD74HCT356 |
유사한 부품 번호 - CD74HCT356E |
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유사한 설명 - CD74HCT356E |
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