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AD9022SZ 데이터시트(PDF) 9 Page - Analog Devices |
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AD9022SZ 데이터시트(HTML) 9 Page - Analog Devices |
9 / 12 page AD9022 REV. B –9– USING THE AD9022 Layout Information Preserving the accuracy and dynamic performance of the AD9022 requires that designers pay special attention to the layout of the printed circuit board. Analog paths should be kept as short as possible and be properly terminated to avoid reflections. The analog input connection should be kept away from digital signal paths; this reduces the amount of digital switching noise, which is capacitively coupled into the analog section. Digital signal paths should also be kept short, and run lengths should be matched to avoid propagation delay mismatch. The AD9022 digital outputs should be buff- ered or latched close to the device (<2 cm). This prevents load transients that may feed back into the device. In high speed circuits, layout of the ground is critical. A single, low impedance ground plane on the component side of the board is recommended. Power supplies should be capacitively coupled to the ground plane with high quality 0.1 µF chip ca- pacitors to reduce noise in the circuit. All power pins of the AD9022 should be bypassed individually. The compensation pin (COMP Pin 17) should be bypassed directly to the –VS supply (Pin 15) as close to the part as possible using a 0.1 µF chip capacitor. Multilayer boards allow designers to lay out signal traces with- out interrupting the ground plane, and provide low impedance ground planes. In systems with dedicated analog and digital grounds, all grounds for the AD9022 should be connected to the analog ground plane. In systems using multilayer boards, dedicated power planes are recommended to provide low impedance connections for device power. Sockets limit dynamic performance and are not recom- mended for use with the AD9022. Timing Conversion by the AD9022 is initiated by the rising edge of the ENCODE clock (Pin 8). All required timing is generated inter- nal to the ADC. Care should be taken to ensure that the encode clock to the AD9022 is free from jitter that can degrade dy- namic performance. The clock driver should be compatible with TTL LS logic series devices. Drivers with excessive slew rate or overdrive will degrade the dynamic performance of the AD9022. Pulsewidth of the ADC encode clock must be controlled to ensure the best possible performance. Dynamic performance is guaranteed with a clock pulse HIGH minimum of 25 ns. Opera- tion with narrower pulses will degrade SNR and dynamic per- formance. From a system perspective, this is generally not a problem, because a simple inverter can be used to generate a suitable clock if the system clock is less than 25 ns wide. The AD9022 provides latched data outputs. Data outputs are available two pipeline delays and one propagation delay after the rising edge of the encode clock (refer to the AD9022 Timing Diagram). The length of the output data lines and the loads placed on them should be minimized to reduce transients within the AD9022; these transients can detract from the converter’s dynamic performance. Operation at encode rates less than 4 MSPS is not recom- mended. The internal track-and-hold saturates, causing errone- ous conversions. This T/H saturation precludes clocking the AD9022 in a burst mode. The duty cycle of the encode clock for the AD9022 is critical for obtaining rated performance of the ADC. Internal pulsewidths within the track-and-hold are established by the encode com- mand pulsewidth; to ensure rated performance, minimum and maximum pulsewidth restrictions should be observed. Operation at 20 MSPS is optimized when the duty cycle is held at 55%. Analog Input The analog input (Pin 12) voltage range is nominally ±1.024 volts. The range is set with an internal voltage reference and cannot be adjusted by the user. The input resistance is 300 Ω and the analog bandwidth is 110 MHz, making the AD9022 useful in undersampling applications. The AD9022 should be driven from a low impedance source. The noise and distortion of the amplifier should be considered to preserve the dynamic range of the AD9022. Power Supplies The power supplies of the AD9022 should be isolated from the supplies used for noisy devices (digital logic especially) to re- duce the amount of noise coupled into the ADC. For optimum performance, linear supplies ensure that switching noise from the supplies does not introduce distortion products during the encoding process. If switching supplies must be used, decoupling recommendations above are critically important. The PSRR of the AD9022 is a function of the ripple frequency present on the supplies. Clearly, power supplies with the lowest possible frequency should be selected. AD9022 EVALUATION BOARD The evaluation board for the AD9022 (AD9022/PCB) provides an easy and flexible method for evaluating the ADC’s perfor- mance without (or prior to) developing a user-specific printed circuit board. The two-sided board includes a reconstruction DAC and digital output interface, and uses the layout and appli- cations suggestions outlined above. It is available at nominal cost from Analog Devices, Inc. Input/Output/Supply Information Power supply, analog input, clock connections and recon- structed output (RC OUTPUT) are identified by labels on the evaluation board. Operation of the evaluation board will conform to the following characteristics: Parameter Typical Units Supply Current +5 V 150 mA –5 V 300 mA AIN Impedance 51 Ω Voltage Range ±1.024 V CLOCK Impedance 51 Ω Frequency 20 MSPS RC OUTPUT Impedance 51 Ω Voltage Range 0 to –1 V |
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