Data Sheet

512 Kbit SPI Serial Flash

SST25VF512

7

©2005 Silicon Storage Technology, Inc.

S71192-08-000

11/05

Auto Address Increment (AAI)

The Auto Address Increment Programming-Status bit pro-

vides status on whether the device is in AAI programming

mode or Byte-Program mode. The default at power up is

Byte-Program mode.

Instructions

Instructions are used to Read, Write (Erase and Program),

and configure the SST25VF512. The instruction bus cycles

are 8 bits each for commands (Op Code), data, and

addresses. Prior to executing any Byte-Program, Auto

Address Increment (AAI) programming, Sector-Erase,

Block-Erase, or Chip-Erase instructions, the Write-Enable

(WREN) instruction must be executed first. The complete

list of the instructions is provided in Table 6. All instructions

are synchronized off a high to low transition of CE#. Inputs

will be accepted on the rising edge of SCK starting with the

most significant bit. CE# must be driven low before an

instruction is entered and must be driven high after the last

bit of the instruction has been shifted in (except for Read,

Read-ID and Read-Status-Register instructions). Any low

to high transition on CE#, before receiving the last bit of an

instruction bus cycle, will terminate the instruction in

progress and return the device to the standby mode.

Instruction commands (Op Code), addresses, and data are

all input from the most significant bit (MSB) first.

TABLE

2. One bus cycle is eight clock periods.

12

3

4

5

Read

03H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

X

6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction

must be executed.

20H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

-

-

Block-Erase5,7

52H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

-

-

Chip-Erase6

60H

Hi-Z

-

-

-

-

-

-

-

-

Byte-Program6

02H

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Auto Address Increment (AAI) Program6,8

8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,

followed by the data to be programmed.

AFH

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Read-Status-Register (RDSR)

05H

Hi-Z

X

9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.

-Note9

-Note9

10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of

each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both

instructions effective.

50H

Hi-Z

-

-

-

-

-

-

-

-

Write-Status-Register (WRSR)10

01H

Hi-Z

Data

Hi-Z

-

-

-.

-

-

-

Write-Enable (WREN)

06H

Hi-Z

-

-

-

-

-

-

-

-

Write-Disable (WRDI)

04H

Hi-Z

-

-

-

-

-

-

-

-

Read-ID

90H or

ABH

Hi-Z

00H

Hi-Z

00H

Hi-Z

ID output stream is continuous until terminated by a low to high transition on CE#

Hi-Z

X

12. Device ID = 48H for SST25VF512

T6.18 1192