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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LFX1200B-03F900C 데이터시트(PDF) 9 Page - Lattice Semiconductor |
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LFX1200B-03F900C 데이터시트(HTML) 9 Page - Lattice Semiconductor |
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9 / 89 page  Lattice Semiconductor ispXPGA Family Data Sheet 9 Set/Reset signal controls all the registers for each PFU. This common Set/Reset signal is composed of the logical OR term of the Global Set/Reset signal (GSR) and the selected signal from routing. The polarity of this signal is not controllable inside the PFU. Figure 9 shows the Clock Enable and Output Enable selection for each PFU. Figure 7. Clock Selection per PFU Figure 8. Set/Reset Selection per PFU Figure 9. Clock Enable and Output Enable Selection per PFU Programmable Input/Output Cell The Programmable Input/Output Cell (PIC) is an essential part of the symmetrical architecture of the ispXPGA Family. The PICs interface the PFUs and EBRs to the sysIO and sysHSI blocks of the device. Each PIC contains two Programmable Input/Outputs (PIOs) with a total of 21 inputs and 10 outputs. There are 18 inputs from routing, two inputs from the sysIO buffers, and the Global Set/Reset signal. Four outputs of the PIC connect to routing and two outputs are available as Output Enables for the tri-statable Long Lines. The remaining four outputs feed the sysIO buffers directly (one output enable and one output to each). Each PIC associated with a sysHSI block has four additional inputs and six additional outputs to support the sysHSI blocks. The four addi- tional inputs come from the sysHSI block associated with the PIC. The four of the six additional outputs come from the PIC outputs and feed the sysHSI block, while the remaining two outputs feed routing. Figure 10 shows the block diagram of the PIC with the sysHSI block inputs and outputs. From routing PFUCLK0 PFUCLK1 CLK0 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 4 From routing Set/Reset GSR 8 CEB1 OE 8 From routing CEB0 8 From routing |
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