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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LFX1200B-4F900I 데이터시트(PDF) 11 Page - Lattice Semiconductor |
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LFX1200B-4F900I 데이터시트(HTML) 11 Page - Lattice Semiconductor |
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11 / 89 page  Lattice Semiconductor ispXPGA Family Data Sheet 11 Figure 11. ispXPGA PIO VLI Routing Resources The ispXPGA architecture contains a Variable-Length-Interconnect (VLI) routing technology connecting the PFUs, PICs, and EBRs in the device. There are four types of routing resources, Global Lines, Long Lines, General Inter- connect, and Local Lines forming the global routing structure. This allows a signal to be routed to any element in the device with the optimal delay. The Global Lines consist of global clock lines and a global set/reset line. These lines are routed to all elements in the device. They are specifically designed for high speed, predictable timing regardless of fan-out. The global clock lines can also be used as dedicated inputs. The Long Lines consist of Horizontal and Vertical Long Lines (HLL and VLL). The VLL and HLL are tri-statable lines spanning the entire device. These lines allow fast routing for high fan-out nets and general-purpose functions. The General Interconnect consists of Double and Deca Lines. The Double Lines connect up to three elements (two plus the driving element), while the Deca Lines connect up to eleven elements (ten plus the driving element). The Local Lines are extremely fast routing paths consisting of Feedback and Direct Connect Lines. The Feedback Lines are internal routing paths from the PFU outputs to the PFU inputs. The Direct Connect Lines connect all adja- cent elements. The Common Interface Block (CIB) provides the link between the logic element (PFU, PIC, or EBR) and the VLI Routing resources. The CIB is a switch matrix that can be programmed to connect virtually any routing resource to any input or output of the logic element. Feed-through (FT) OUT0 Clock (CLK) Input Clock Enable (ICEN) Input Set/Reset (ISR) Global Set/Reset(GSR) Output Clock Enable (OCEN) PIO Input (IN) Output Set/Reset (OSR) PIO Output Enable(OEN) PIO Input Enable (IEN) OUT1 Delay OE From sysIO Input To sysIO Output Enable To sysIO Output CE DQ SR CLK/LE CE DQ SR CLK/LE CE DQ SR CLK/LE From sysHSI block From sysHSI block To Routing To sysHSI block To sysHSI block Only for PIOs associated with sysHSI Blocks Only for PIOs Associated with sysHSI Blocks |
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