FM25256 datasheet(6/13 Pages) ETC

부품명	FM25256

상세설명	256Kb FRAM Serial 5V Memory

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FM25256

Rev. 2.0

Apr. 2005

Page 6 of 13

CS

SCK

SI

SO

Hi-Z

0

1

2

3

4

5

6

7

0

1

0

Figure 6. WRDI Bus Configuration

RDSR - Read Status Register

The RDSR command allows the bus master to verify

the contents of the Status register. Reading Status

provides information about the current state of the

write protection features. Following the RDSR op-

code, the FM25256 will return one byte with the

contents of the Status register. The Status register is

described in detail in a later section.

WRSR – Write Status Register

The WRSR command allows the user to select

certain write protection features by writing a byte to

the Status register. Prior to issuing a WRSR

command, the /WP pin must be high or inactive.

Prior to sending the WRSR command, the user must

send a WREN command to enable writes. Note that

executing a WRSR command is a write operation

and therefore clears the Write Enable Latch.

Figure 7. RDSR Bus Configuration

Figure 8. WRSR Bus Configuration

Status Register & Write Protection

The write protection features of the FM25256 are

multi-tiered. Taking the /WP pin to a logic low state

is the hardware write protect function. All write

operations are blocked when /WP is low. To write the

memory with /WP high, a WREN op-code must first

be issued. Assuming that writes are enabled using

WREN and by /WP, writes to memory are controlled

by the Status register. As described above, writes to

the status register are performed using the WRSR

command and subject to the /WP pin. The Status

register is organized as follows.

Table 2. Status Register

Bit

7

6

5

4

3

2

1

0

Name

WPEN

0

BP1

BP0

WEL

0

Bits 0 and 4-6 are fixed at 0 and cannot be modified.

Note that bit 0 (Ready in EEPROMs) is unnecessary

as the FRAM writes in real-time and is never busy.

The BP1 and BP0 control software write protection

features. They are nonvolatile (shaded yellow). The

WEL flag indicates the state of the Write Enable

Latch. Attempting to directly write the WEL bit in

the status register has no effect on its state. This bit

is internally set by the WREN command and cleared

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