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IDT7035L 데이터시트(PDF) 14 Page - Integrated Device Technology |
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IDT7035L 데이터시트(HTML) 14 Page - Integrated Device Technology |
14 / 19 page 6.42 IDT7035S/L High-Speed 8K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 14 Wa ve for m of I nt e r rupt T im ing(1) Trut h Ta ble I I I — I nt e r rupt Fla g(1,2) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”. 2. See Interrupt Flag Truth Table III. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. NOTES: 1. Assumes BUSYL = BUSYR = VIH. 2. If BUSYL = VIL, then no change. 3. If BUSYR = VIL, then no change. 4. INTR and INTL must be initialized at power-up. 4088 drw 15 ADDR"A" INTERRUPT SET ADDRESS CE"A" R/W"A" tAS tWC tWR (3) (4) tINS (3) INT"B" (2) 4088 drw 16 ADDR"B" INTERRUPT CLEAR ADDRESS CE"B" OE"B" tAS tRC (3) tINR (3) INT"B" (2) Left Port Right Port Function R/WL CEL OEL A0L-A12L INTL R/WR CER OER A0R-A12R INTR LL X 1FFF X X X X X L(2) Set Right INTR Flag X X XXX X L L 1FFF H(3) Reset Right INTR Flag XX X X L(3) L L X 1FFE X Set Left INTL Flag X L L 1FFE H(2) X X X X X Reset Left INTL Flag 4088 tbl 16 |
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