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DM9102D 데이터시트(PDF) 11 Page - List of Unclassifed Manufacturers

부품명 DM9102D
상세설명  SINGLE CHIP FAST ETHEMET NIC CONTROLLER
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Preliminary datasheet
11
Version: DM9102D-DS-P02
Jan. 14, 2005
6. Register Definition
6.1 PCI Configuration Registers
The definitions of PCI Configuration Registers are based on
the PCI specification revision 2.2 and it provides the
initialization and configuration information to operate the PCI
interface in the DM9102D. All registers can be accessed
with byte, word, or double word mode. As defined in PCI
specification
2.1,
read
accesses
to
reserve
or
unimplemented registers will return a value of “0.” These
registers are to be described in the following sections.
The default value of PCI configuration registers after reset.
Description
Identifier
Address Offset
Value of Reset
Identification
PCIID
00H
91021282H
Command & Status
PCICS
04H
02100000H*
Revision
PCIRV
08H
02000050H
Miscellaneous
PCILT
0CH
BIOS determine
I/O Base Address
PCIIO
10H
System allocate
Memory Base Address
PCIMEM
14H
System allocate
Reserved
--------
18H - 28H
00000000H
Subsystem Identification
PCISID
2CH
load from EEPROM
Expansion ROM Base Address
PCIROM
30H
00000000H
Capability Pointer
CAP_PTR
34H
00000050H
Reserved
--------
38H
00000000H
Interrupt & Latency
PCIINT
3CH
System allocate bit7~0
Device Specific Configuration Register
PCIUSR
40H
00000000H**
Power Management Register
PCIPMR
50H
C0310001H**
Power Management Control & Status
PMCSR
54H
00000100H
* It is written to 02100007H by most BIOS.
** It may be changed from EEPROM in application.
Key to Default
In the register description that follows, the default column
takes the form <Reset Value>
Where:
<Reset Value>:
1
Bit set to logic one
0
Bit set to logic zero
X
No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C: means Read / Write & Write "1" for Clear.


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