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1 / 4 page 1998 © Document No. D16163EJ1V0DS00 (1st edition) Date Published April 2002 N CP(K) Printed in Japan COMPOUND TRANSISTOR AA1L3N on-chip resistor NPN silicon epitaxial transistor For mid-speed switching DATA SHEET 2002 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. FEATURES • On-chip bias resistor (R1 = 4.7 k Ω, R2 = 10 kΩ) • Complementary transistor with AN1L3N ABSOLUTE MAXIMUM RATINGS (Ta = 25 °°°°C) Parameter Symbol Ratings Unit Collector to base voltage VCBO 60 V Collector to emitter voltage VCEO 50 V Emitter to base voltage VEBO 5V Collector current (DC) IC(DC) 100 mA Collector current (Pulse) IC(pulse) * 200 mA Total power dissipation PT 250 mW Junction temperature Tj 150 °C Storage temperature Tstg −55 to +150 °C *PW ≤ 10 ms, duty cycle ≤ 50 % PACKAGE DRAWING (UNIT: mm) ELECTRICAL CHARACTERISTICS (Ta = 25 °°°°C) Parameter Symbol Conditions MIN. TYP. MAX. Unit Collector cutoff current ICBO VCB = 50 V, IE = 0 100 nA DC current gain hFE1 ** VCE = 5.0 V, IC = 5.0 mA 35 60 100 − DC current gain hFE2 ** VCE = 5.0 V, IC = 50 mA 80 230 − Collector saturation voltage VCE(sat) ** IC = 5.0 mA, IB = 0.25 mA 0.05 0.2 V Low level input voltage VIL ** VCE = 5.0 V, IC = 100 µA 0.9 0.6 V High level input voltage VIH ** VCE = 0.2 V, IC = 5.0 mA 3.0 1.5 V Input resistance R1 3.29 4.7 6.11 k Ω E-to-B resistance R2 710 13 k Ω Turn-on time ton 0.2 µs Storage time tstg 5.0 µs Turn-off time toff VCC = 5 V, RL = 1 k Ω VI = 5 V, PW = 2 µs duty cycle ≤2 % 6.0 µs ** Pulse test PW ≤ 350 µs, duty cycle ≤ 2 % |
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