전자부품 데이터시트 검색엔진 |
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93C66CTIPG 데이터시트(PDF) 9 Page - Microchip Technology |
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93C66CTIPG 데이터시트(HTML) 9 Page - Microchip Technology |
9 / 24 page 2003 Microchip Technology Inc. DS21795B-page 9 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C 2.8 WRITE The WRITE instruction is followed by 8 bits (If ORG is low or A-version devices) or 16 bits (If ORG pin is high or B-version devices) of data which are written into the specified address. For 93AA66A/B/C and 93LC66A/B/C devices, after the last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C66A/B/C devices, the self- timed auto-erase and programming cycle is initiated by the rising edge of CLK on the last data bit. The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. Note: Issuing a Start bit and then taking CS low will clear the READY/BUSY status from DO. FIGURE 2-8: WRITE TIMING FOR 93AA AND 93LC DEVICES FIGURE 2-9: WRITE TIMING FOR 93C DEVICES CS CLK DI DO 1 0 1An ••• A0 Dx ••• D0 BUSY READY HIGH-Z HIGH-Z Twc TCSL TCZ TSV CS CLK DI DO 1 0 1An ••• A0 Dx ••• D0 BUSY READY HIGH-Z HIGH-Z Twc TCSL TCZ TSV |
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