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AM30LV0064DJ40WGIT 데이터시트(PDF) 10 Page - Advanced Micro Devices |
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AM30LV0064DJ40WGIT 데이터시트(HTML) 10 Page - Advanced Micro Devices |
10 / 41 page 10 Am30LV0064D FUNCTIONAL PIN DESCRIPTION Input/Output Pins (I/O7–I/O0) The eight I/O pins are used to send commands, ad- dresses, and data to the device, and to receive data during read operations. Command Latch Enable (CLE) The CLE input controls activation of the command reg- ister for the receipt of commands. When CLE is high, the command is latched into the command register on the rising edge of the Write Enable (WE#) signal. Address Latch Enable (ALE) The ALE input controls activation of the address register during the address latch operation, or the data register during the Input Data operation. When ALE is high, the address information is latched on the rising edge of the Write Enable (WE#) signal. When ALE is low (and the CLE input is low) the Input Data information is latched on the rising edge of the Write Enable (WE#) signal. ALE must remain high for the entire address sequence or device will reset. Chip Enable (CE#) The CE# input controls the active/standby mode dur- ing command, data, and address inputs. During the command and address latch operations, CE# must be low prior to the falling edge of Write Enable (WE#). During Input Data operations, CE# must remain low until after the rising edge of WE# during the final Data In operation. When CE# is high, and an internal opera- tion is not in process, the device goes into standby mode and current consumption is greatly reduced. The CE# signal is ignored during program or erase op- eration, as indicated by the Busy state (RY/BY# = low). Read Enable (RE#) The RE# input controls the serial data output and sta- tus from the I/O lines. The data output is triggered on the falling edge of RE#, with valid data available after a delay of tREA. The Status output data is also triggered on the falling edge of RE#, with the status available after a delay of tRLS. Write Enable (WE#) The WE# input is used to control the Data/Command on the I/O lines during write operations. The I/O lines are latched on the rising edge of the WE# signal. Write Protect (WP#) The WP# input provides protection from inadvertent program/erase commands. The internal voltage regu- lator is reset when WP# is low, thereby preventing any program or erase operations from occurring. The WP# input should be kept low (VIL) during pow er-up until VCC is above VCC-min. During power-down WP# should be driven low (VIL) before VCC is below VCC-min. Spare Area Enable (SE#) The SE# input controls access to the 16 bytes of spare area on each page. When SE# is not asserted (high), the spare area for the selected page is not enabled, and all input or output data is directed towards the pri- mary 512 byte storage space. When SE# is asserted (low), access to the spare area is enabled, and data can be transferred to or from the 16 bytes of spare area for the appropriate page as needed. With SE# asserted (low) information can still be transferred to or from the 512 byte main Flash page, but when the end of the page is reached (byte 511) the device will auto- matically begin transferring information to or from the spare area. During the Read Spare Area command sequence (50h) the SE# input must be asserted (low) during the command phase (CLE high). In all other cases when the spare area is to be accessed, the SE# input must be asserted (low) at least two access cycles prior to the spare area access. This would require the SE# input to be low by the time byte address 510 is se- lected, and SE# must remain low during the entire period that the spare area is accessed. Ready/Busy Output (RY/BY#) The RY/BY# output indicates the operation status of the device. When RY/BY# is high, the device is ready to accept the next operation. When RY/BY# is low, an internal program, erase, or random read operation is in progress. RY/BY# is an open drain output pin which allows multi- ple RY/BY# pins to be wire-ORed together. The RY/BY# output pin requires an external pull-up resistor to VCC (or VCCQ) for proper operation. Device Power Supply (VCC) The mi ni mum V CC op erat in g v oltag e for th e Am30LV0064D is 2.7 volts. The device has an operat- ing voltage range from 2.7 volts to 3.6 volts. Output Buffer Power Supply (VCCQ) The output voltage generated on the device is deter- mined based on the VCCQ power supply input level. A VCCQ of 2.7 to 3.6 volts will allow the device to function as a 3.0 Volt-only device. A VCCQ of 4.5 to 5.5 volts provides 5 volt I/O tolerance. All input only signals are 5 volt tolerant by design, in- dependent of the voltage on VCCQ. Ground (VSS) The VSS pins on the device must be grounded. |
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