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MC100ES6017DWR2 데이터시트(PDF) 1 Page - Freescale Semiconductor, Inc |
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MC100ES6017DWR2 데이터시트(HTML) 1 Page - Freescale Semiconductor, Inc |
1 / 6 page Document Number: MC100ES6017 Rev 2, 09/2005 Freescale Semiconductor Technical Data © Freescale Semiconductor, Inc., 2005. All rights reserved. 3.3 V ECL/PECL Quad Differential Receiver The MC100ES6017 is a 3.3 V ECL/PECL quad differential receiver. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled down to VEE. This operation will force the Q output LOW and ensure stability. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features • High bandwidth output transitions • LVPECL operating range: VCC = 3.0 V to 3.6 V • Internal input pulldown resistors on D inputs, pullup and pulldown resistors on D inputs • 20 lead SOIC package • Ambient temperature range -40°C to +85°C • 20-lead Pb-free package available MC100ES6017 ECL/PECL QUAD DIFFERENTIAL RECEIVER DW SUFFIX 20-LEAD SOIC PACKAGE CASE 751D-07 ORDERING INFORMATION Device Package MC100ES6017DW SO-20 MC100ES6017DWR2 SO-20 MC100ES6017EG SO-20 (Pb-Free) MC100ES6017EGR2 SO-20 (Pb-Free) PIN DESCRIPTION Pin Function Dn, Dn ECL Differential Data Inputs Qn, Qn ECL Differential Data Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply EG SUFFIX 20-LEAD SOIC PACKAGE Pb-FREE PACKAGE CASE 751D-07 Figure 1. 20-Lead Pinout (Top View) and Logic Diagram 1 20 19 18 17 16 15 14 13 2 3 6 VCC VCC D0 D0 D1 D1 Q0 Q3 Q1 Q0 Q2 Q2 4 Q1 5 78 D2 D3 VBB 910 12 11 VEE Q3 D2 D3 |
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