전자부품 데이터시트 검색엔진 |
|
MAX2121B 데이터시트(PDF) 15 Page - Maxim Integrated Products |
|
MAX2121B 데이터시트(HTML) 15 Page - Maxim Integrated Products |
15 / 20 page 2-Wire Serial Interface The MAX2121B uses a 2-wire I2C-compatible serial inter- face consisting of a serial-data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communi- cation between the MAX2121B and the master at clock fre- quencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX2121B behaves as a slave device that transfers and receives data to and from the master. SDA and SCL must be pulled high with external pullup resistors (1kΩorgreater)forproperbusoperation.Pullupresistors should be referenced to the MAX2121B’s VCC. One bit is transferred during each SCL clock cycle. A mini- mum of nine clock cycles is required to transfer a byte in or out of the MAX2121B (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condi- tion (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX2121B (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge- related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. Slave Address The MAX2121B has a 7-bit slave address that must be sent to the device following a START condition to initiate com- munication. The slave address is internally programmed to 1100000. The eighth bit (R/W) following the 7-bit address determines whether a read or write operation occurs. The MAX2121B continuously awaits a START condition followed by its slave address. When the device recog- nizes its slave address, it acknowledges by pulling the SDA line low for one clock period; it is ready to accept or send data depending on the R/W bit (Figure 1). The write/read address is C0/C1 if ADDR pin is connected to ground. The write/read address is C2/C3 if the ADDR pin is connected to VCC. Write Cycle When addressed with a write command, the MAX2121B allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX2121B issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to (see Table 1 for regis- ter addresses). If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX2121B again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal reg- isters with the MAX2121B acknowledging each success- ful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition. Figure 1. MAX2121B Slave Address Byte with ADDR Pin Connected to Ground Figure 2. Example: Write Registers 0, 1, and 2 with 0x0E, 0xD8, and 0xE1, respectively. WRITE DEVICE ADDRESS R/W ACK WRITE REGISTER ADDRESS AC WRITE DATA TO REGISTER 0x00 ACK WRITE DATA TO REGISTER 0x01 ACK WRITE DATA TO REGISTER 0x02 ACK START 1100000 0 — 0x00 — 0x0E — 0xD8 — 0xE1 — STOP SCL 1 2 3 4 5 6 7 1 1 0 0 0 0 0 8 9 R/W ACK SLAVE ADDRESS S SDA MAX2121B L-Band Tuner with Programmable Baseband Filter www.maximintegrated.com Maxim Integrated │ 15 |
유사한 부품 번호 - MAX2121B |
|
유사한 설명 - MAX2121B |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |