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GD25B64C 데이터시트(PDF) 29 Page - GigaDevice Semiconductor (Beijing) Inc.

부품명 GD25B64C
상세설명  3.3V Uniform Sector Dual and Quad Serial Flash
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제조업체  GIGADEVICE [GigaDevice Semiconductor (Beijing) Inc.]
홈페이지  http://www.gigadevice.com/
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3.3V Uniform Sector
Dual and Quad Serial Flash
GD25B64C
29
7.18. 32KB Block Erase (BE) (52H)
The 32KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 32KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address
inside the block is a valid address for the 32KB Block Erase (BE) command. CS# must be driven low for the entire duration
of the sequence.
The 32KB Block Erase command sequence: CS# goes low  sending 32KB Block Erase command  3-byte
address on SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of
the last address byte has been latched in; otherwise the 32KB Block Erase (BE) command is not executed. As soon as
CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A 32KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 21. 32KB Block Erase Sequence Diagram
7.19. 64KB Block Erase (BE) (D8H)
The 64KB Block Erase (BE) command is used to erase all the data of the chosen block. A Write Enable (WREN)
command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE)
command is entered by driving CS# low, followed by the command code, and three address bytes on SI. Any address
inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration
of the sequence.
The 64KB Block Erase command sequence: CS# goes low  sending 64KB Block Erase command  3-byte
address on SI  CS# goes high. The command sequence is shown below. CS# must be driven high after the eighth bit of
the last address byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as
CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in
progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress
(WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which
is protected by the Block Protect (BP4, BP3, BP2, BP1, and BP0) bits (see Table1&1a) is not executed.
Figure 22. 64KB Block Erase Sequence Diagram
Command
0
1
2
3
4
5
6
7
52H
CS#
SCLK
SI
8
9
29 30 31
MSB
2
1
0
24 Bits Address
23 22
Command
0
1
2
3
4
5
6
7
D8H
CS#
SCLK
SI
8
9
29 30 31
MSB
2
1
0
24 Bits Address
23 22


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