전자부품 데이터시트 검색엔진 |
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GD25B256D 데이터시트(PDF) 15 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B256D 데이터시트(HTML) 15 Page - GigaDevice Semiconductor (Beijing) Inc. |
15 / 82 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25B256D 15 6.2. Extended Address Register Table 12 Extended Address Register No. Name Description Note EA0 A24 Address bit Volatile writable EA1 Reserved Reserved Reserved EA2 Reserved Reserved Reserved EA3 Reserved Reserved Reserved EA4 Reserved Reserved Reserved EA5 Reserved Reserved Reserved EA6 Reserved Reserved Reserved EA7 Reserved Reserved Reserved The extended address register is only used when the address mode is 3-Byte mode, as to set the higher address. A24=1 indicates the upper 128Mb memory address, A24=0 indicates the lower 128Mb. EA1~EA7 are reserved. A24 bit The Extended Address Bit A24 is used only when the device is operating in the 3-Byte Address Mode (ADS=0), which is volatile writable by C5H command. The lower 128Mb memory array (00000000h – 00FFFFFFh) is selected when A24=0, and all instructions with 3-Byte addresses will be executed within that region. When A24=1, the upper 128Mb memory array (01000000h – 01FFFFFFh) will be selected. If the device powers up with ADP bit set to 1, or an “Enter 4-Byte Address Mode (B7H)” instruction is issued, the device will require 4-Byte address input for all address related instructions, and the Extended Address Bit A24 setting will be ignored. However, any instruction with 4-Byte address input will replace the Extended Address Bit A24 with new settings. Reserved bit It is recommended to set the value of the reserved bit as “0”. |
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