SN74AUC16501DGVR datasheet(7/13 Pages) TI

부품명	SN74AUC16501DGVR

상세설명	18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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Operating Characteristics

(1)

SN74AUC16501

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES418 – DECEMBER 2002 – REVISED JUNE 2005

for clocked mode, T

A = 25°C

VCC = 0.8 V

VCC = 1.2 V

VCC = 1.5 V

VCC = 1.8 V

VCC = 2.5 V

TEST

PARAMETER

UNIT

CONDITIONS

TYP

1 fdata = 5 MHz,

1 fclk = 10 MHz,

Outputs

Cpd

Power

1 fout = 5 MHz,

enabled, 1

(each

dissipation

OEAB = VCC,

29

30

31

35

43

pF

output

bit)(2)

capacitance

OEBA = GND,

switching

LE = GND,

CL = 0 pF

1 fdata = 5 MHz,

1 fclk = 10 MHz,

Outputs

fout = not

Power

disabled,

switching,

Cpd(Z)

dissipation

1 clock

8

9

10

13

pF

OEAB = GND,

capacitance and 1 data

OEBA = VCC,

switching

LE = GND,

CL = 0 pF

1 fdata = 0 MHz,

1 fclk = 10 MHz,

Outputs

fout = not

Cpd

Power

disabled,

switching,

(each

dissipation

31

32

34

39

pF

clock only

OEAB = GND,

clock)(3)

capacitance

switching

OEBA = VCC,

LE = GND,

CL = 0 pF

(1)

Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}

(2)

Cpd (each bit) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (the clock is operating at 10 MHz in this

test, but its ICC component has been subtracted out).

(3)

Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.

7

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