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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M30L0R8000B0ZAQ 데이터시트(PDF) 17 Page - STMicroelectronics |
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M30L0R8000B0ZAQ 데이터시트(HTML) 17 Page - STMicroelectronics |
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17 / 83 page  17/83 M30L0R8000T0, M30L0R8000B0 See APPENDIX C., Figure 21., Buffer Program Flowchart and Pseudo Code, for a suggested flow- chart on using the Buffer Program command. Buffer Enhanced Factory Program Command The Buffer Enhanced Factory Program command has been specially developed to speed up pro- gramming in manufacturing environments where the programming time is critical. It is used to program one or more Write Buffer(s) of 32 Words to a block. Once the device enters Buffer Enhanced Factory Program mode, the Write Buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. The use of the Buffer Enhanced Factory Program command requires certain operating conditions: ■ VPP must be set to VPPH ■ VDD must be within operating range ■ Ambient temperature TA must be 30°C ± 10°C ■ The targeted block must be unlocked ■ The start address must be aligned with the start of a 32 Word buffer boundary ■ The address must remain the Start Address throughout programming. Dual operations are not supported during the Buff- er Enhanced Factory Program operation and the command cannot be suspended. If the block is protected, the Buffer Enhanced Fac- tory Program operation will abort, the data in the block will not be changed and the Status Register will output the error. The Buffer Enhanced Factory Program Command consists of three phases: the Setup Phase, the Program and Verify Phase, and the Exit Phase, Please refer to Table 6., Factory Program Com- mand for detail information. Setup Phase. The Buffer Enhanced Factory Pro- gram command requires two Bus Write cycles to initiate the command. ■ The first Bus Write cycle sets up the Buffer Enhanced Factory Program command. ■ The second Bus Write cycle confirms the command. After the confirm command is issued, read opera- tions output the contents of the Status Register. The read Status Register command must not be issued as it will be interpreted as data to program. The Status Register P/E.C. Bit SR7 should be read to check that the P/E.C. is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program opera- tion is terminated. See Status Register section for details on the error. Program and Verify Phase. The Program and Verify Phase requires 32 cycles to program the 32 Words to the Write Buffer. The data is stored se- quentially, starting at the first address of the Write Buffer, until the Write Buffer is full (32 Words). To program less than 32 Words, the remaining Words should be programmed with FFFFh. Three successive steps are required to issue and execute the Program and Verify Phase of the com- mand. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address must remain the Start Address as the P/E.C. increments the address location.If any address that is not in the same block as the Start Address is given, the Program and Verify Phase terminates. Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Once the Write Buffer is full, the data is pro- grammed sequentially to the memory array. After the program operation the device auto- matically verifies the data and reprograms if necessary. The Program and Verify phase can be repeated, without re-issuing the command, to program addi- tional 32 Word locations as long as the address re- mains in the same block. 4. Finally, after all Words, or the entire block have been programmed, write one Bus Write operation to any address outside the block containing the Start Address, to terminate Program and Verify Phase. Status Register bit SR0 must be checked to deter- mine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed. Exit Phase. Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has exited the Buffer Enhanced Factory Program operation and re- turned to Read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. |
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