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This document contains preliminary information. Information is subject to change without notice.
TC3000 is covered by several patents.
Flexibility
TC3000 family offers 3 levels of flexibility :
TC3000 family member
9 BCH t=2 code support (YES/NO)
9 Choice on bitrate
VHDL generic parameters
before synthesis
9 Maximum row code length
9 Maximum column code length
9 Input Quantization width
9 1 or 2 input buffers
On-the fly parameters
from block to block
9 Row code
9 Column code
9 Shortening values
9 Max. number of iterations
9 Stopping feature enabled
FEC performance
Very high FEC performance are obtained for various block sizes and coding rates. The FEC behaviour
of the “BCH t=2” codes makes them particularly attractive for quasi-error free applications.
Ö Gaussian channel and QPSK modulation. Results given with 5 iterations.
Product Code
Rate
Eb/N0 @BER=10
-5
Eb/N0 @BER=10
-8
(32,26) x (32,26)
0.660
2.9 dB
3.6 dB
(32,21) x (32,21)
0.431
2.4 dB
N.A.
(64,57) x (64,57)
0.793
3.2 dB
3.6 dB
(64,51) x (64,51)
0.635
2.6 dB
2.9 dB
(128,120) x (128,120) 0.879
3.8 dB
4.2 dB
(128,113) x (128,113) 0.779
3.3 dB
3.4 dB
(256,247) x (256,247) 0.931
4.5 dB
4.8 dB
(256,239) x (256,239) 0.872
4.0 dB
N.A.
Block Diagram
Implementation results
Codes supported
Generic parameter setting
Implementation results
Product
Hamming
BCH t=2
Row max.
length
Column
max. length
Data
width
bank
swap
LE
ESB
APEX20K
device
Fmax
MHz
Typical Bitrate
@(64,57)², 5 iterations
TC3011
9
64
64
4
NO
2025
22
200 C7
82
8 Mbits/s
64
64
4
NO
6926
36
200 C7
72
25 Mbits/s
TC3014
9
128
128
4
NO
8115
88
400 C7
67
23.5 Mbits/s
TC3022
9
9
64
64
4
NO
8932
24
400 C7
79
14 Mbits/s
Decoder
module
Configuration module
D[D_WIDTH-1:0]
DEN
DBLK
TC3000
DRDY
DCK
Input
Interface
CK
RSTB
MSELECT
Q
QEN
QBLK
QRDY
QCK
Global
Signals
Input
Buffer #1
Input
Buffer #0
Output
Interface
Dedicated
Configuration
I/Os
Microcontroller
Interface
Output
module
Output
Buffer
Input
module
Decoder
module
Configuration module
D[D_WIDTH-1:0]
DEN
DBLK
TC3000
DRDY
DCK
Input
Interface
CK
RSTB
MSELECT
CK
RSTB
MSELECT
Q
QEN
QBLK
QRDY
QCK
Global
Signals
Input
Buffer #1
Input
Buffer #0
Output
Interface
Dedicated
Configuration
I/Os
Microcontroller
Interface
Output
module
Output
Buffer
Input
module