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FM24C16A
Rev 0.1
June 2002
Page 11 of 13
Diagram Notes
All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read
and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional
relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only.
Read Bus Timing
t
SU:SDA
Start
t
R
t
F
Stop Start
t
BUF
t
HIGH
1/fSCL
t
LOW
t
SP
t
SP
Acknowledge
t
HD:DAT
t
SU:D AT
t
AA
t
DH
SCL
SDA
Write Bus Timing
t
SU:STO
Start
Stop Start
Acknowledge
t
AA
t
HD:DAT
t
HD:STA
t
SU:DAT
SCL
SDA
Data Retention (VDD = 4.5V to 5.5V unless otherwise specified)
Parameter
Min
Units
Notes
Data Retention
10
Years
1
Notes
1.
The relationship between retention, temperature, and the associated reliability
level is characterized in a separate reliability report.
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