D1

Q8

D0 VCCO

Q0 VCCO

Q7 VCCO

VCCO

D8

D7

D6

D5

D4

D3

VEE

LEN

MR

D2

26

27

28

2

3

4

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

5

6

7

8

9

10

Q6

Q5

VCC

Q4

Q3

VCCO

Q2

Q1

LOGIC DIAGRAM

D0

D8

LEN

MR

Q0

Q8

ODDPAR

BITS

1–7

D

EN

Q

R

D

EN

Q

R

D

EN

Q

R

1

Pinout: 28-Lead PLCC (Top View)

* All VCC and VCCO pins are tied together on the die.

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

12/93

9Bit Latch With Parity

The MC10E/100E175 is a 9-bit latch. It also features a tenth latched

output, ODDPAR, which is formed as the odd parity of the nine data

inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH).

The E175 can also be used to generate byte parity by using D8 as the

parity-type select (L = even parity, H = odd parity), and using ODDPAR as

the byte parity output.

The LEN pin latches the data when asserted with a logical high and

makes the latch transparent when placed at a logic low level.

PIN NAMES

Pin

Function

D0 – D8

Data Inputs

LEN

Latch Enable

MR

Master Reset

Q0 – Q8

Data Outputs

ODDPAR

Parity Output

MC10E175

MC100E175

9-BIT LATCH

WITH PARITY

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02