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BS616UV4016 데이터시트(Datasheet) 4 Page - Brilliance Semiconductor

부품명 BS616UV4016
상세내용  Ultra Low Power/High Speed CMOS SRAM 256K X 16 Bit
PDF  10 Pages
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제조사  BSI [Brilliance Semiconductor]
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BSI
BS616UV4016
4
R0201-BS616UV4016
Revision
1.3
Sep.
2005
n DATA RETENTION CHARACTERISTICS (T
A = -40
OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
(1)
MAX.
UNITS
VDR
VCC for Data Retention
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
1.2
--
--
V
ICCDR
(3)
Data Retention Current
CE≧VCC-0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
--
0.15
1.7
uA
tCDR
Chip Deselect to Data
Retention Time
0
--
--
ns
tR
Operation Recovery Time
See Retention Waveform
tRC
(2)
--
--
ns
1. VCC=1.2V, TA=25
OC.
2. tRC = Read Cycle Time.
3. ICCRD_Max. is 1.2uA at TA=70
OC.
n LOW V
CC DATA RETENTION WAVEFORM (1) (CE Controlled)
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
Output Load
Others
CL = 30pF+1TTL
1. Including jig and scope capacitance.
n KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM
“H” TO “L”
WILL BE CHANGE
FROM
“H” TO “L”
MAY CHANGE
FROM
“L” TO “H”
WILL BE CHANGE
FROM
“L” TO “H”
DON
’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
DOES NOT
APPLY
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL
(1)
1 TTL
Output
ALL INPUT PULSES
→ ←
90%
VCC
GND
Rise Time:
1V/ns
Fall Time:
1V/ns
90%
→ ←
10%
10%
Data Retention Mode
VCC
tCDR
VCC
tR
VIH
VIH
CE≧VCC - 0.2V
VDR≧1.0V
CE
VCC




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