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MC10E445 데이터시트(PDF) 5 Page - ON Semiconductor |
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MC10E445 데이터시트(HTML) 5 Page - ON Semiconductor |
5 / 8 page MC10E445 MC100E445 5 MOTOROLA ECLinPS and ECLinPS Lite DL140 — Rev 4 APPLICATIONS INFORMATION The MC10E/100E445 is an integrated 1:4 serial to parallel converter. The chip is designed to work with the E446 device to provide both transmission and receiving of a high speed serial data path. The E445, can convert up to a 2.0Gb/s NRZ data stream into 4-bit parallel data. The device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. The E445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the E446. Figure 4 illustrates the loop test architecture. The architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. The SINA serial input of the E445 has an extra buffer delay and thus should be used as the loop back serial input. SINB SINB SINA SINA SOUT SOUT PARALLEL DATA PARALLEL DATA TO SERIAL MEDIUM FROM SERIAL MEDIUM Figure 4. Loopback Test Architecture The E445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. Figure 5 illustrates the architecture for a 1:8 demultiplexer using two E445’s; the timing diagram for this configuration can be found on the following page. Notice the serial outputs (SOUT) of the lower order converter feed the serial inputs of the the higher order device. This feed through of the serial inputs bounds the upper end of the frequency of operation. The clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. Using the worst case values for these two parameters from the data sheet, TPD CLK to SOUT = 1150ps and tS for SIN = –100ps, yields a minimum period of 1050ps or a clock frequency of 950MHz. The clock frequency is significantly lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order E445. By delaying the clock feeding the second E445 relative to the clock of the first E445 the frequency of operation can be increased. The delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (Figure 6). Q3 Q7 Q2 Q6 Q1 Q5 Q0 Q4 SIN SIN SOUT SOUT E445a Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 SIN SIN E445b CLOCK CLOCK SERIAL INPUT DATA PARALLEL OUTPUT DATA 800ps 1150ps 100ps CLOCK Tpd CLK to SOUT Figure 5. Cascaded 1:8 Converter Architecture With a minimum delay of 800ps on this output the clock for the lower order E445 cannot be delayed more than 800ps relative to the clock of the first E445 without potentially missing a bit of information. Because the setup time on the serial input pin is negative coincident excursions on the data and clock inputs of the E445 will result in correct operation. Figure 6. Cascade Frequency Limitation 800ps 1150ps CLOCK B Tpd CLK to SOUT CLOCK A |
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