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MC10EP35DR2 데이터시트(PDF) 1 Page - ON Semiconductor |
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MC10EP35DR2 데이터시트(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 1999 September, 1999 – Rev. 1.0 1 Publication Order Number: MC10EP35/D MC10EP35 JK Flip Flop The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The J/K data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. • 300ps Propagation Delay • High Bandwidth to 3 GHz Typical • High Bandwidth Output Transistors • PECL mode: 3.0V to 5.5V VCC with VEE = 0V • ECL mode: 0V VCC with VEE = –3.0V to –5.5V • 75kW Internal Input Pulldown Resistors • Q Output will default LOW with inputs open or at VEE • ESD Protection: >4KV HBM, >200V MM • Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D • Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34 • Transistor Count = 77 devices 1 2 3 45 6 7 8 Q VEE VCC Figure 1. 8–Lead Pinout (Top View) and Logic Diagram K Q CLK RESET J J K R Flip Flop SO–8 D SUFFIX CASE 751 PIN DESCRIPTION PIN CLK J, K ECL Signal Inputs FUNCTION ECL Clock Inputs http://onsemi.com RESET ECL Asynchronous Reset Q, Q ECL Data Outputs TRUTH TABLE J L L H H X K L H L H X RESET L L L L H CLK Z Z Z Z X Qn+1 Qn L H Qn L Z = LOW to HIGH Transition MARKING DIAGRAM Device Package Shipping ORDERING INFORMATION MC10EP35D SOIC 98 Units/Rail MC10EP35DR2 SOIC 2500 Tape & Reel HEP35 1 8 ALYW 1 8 A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D |
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