전자부품 데이터시트 검색엔진 |
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MC14022B 데이터시트(PDF) 1 Page - ON Semiconductor |
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MC14022B 데이터시트(HTML) 1 Page - ON Semiconductor |
1 / 8 page © Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 1 Publication Order Number: MC14022B/D MC14022B Octal Counter The MC14022B is a four–stage Johnson octal counter with built–in code converter. High–speed operation and spike–free outputs are obtained by use of a Johnson octal counter design. The eight decoded outputs are normally low, and go high only at their appropriate octal time period. The output changes occur on the positive–going edge of the clock pulse. This part can be used in frequency division applications as well as octal counter or octal decode display applications. • Fully Static Operation • DC Clock Input Circuit Allows Slow Rise Times • Carry Out Output for Cascading • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4022B • Triple Diode Protection on All Inputs MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol Parameter Value Unit VDD DC Supply Voltage Range – 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. http://onsemi.com A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week Device Package Shipping ORDERING INFORMATION MC14022BCP PDIP–16 2000/Box MC14022BD SOIC–16 2400/Box MC14022BDR2 SOIC–16 2500/Tape & Reel MARKING DIAGRAMS 1 16 PDIP–16 P SUFFIX CASE 648 MC14022BCP AWLYYWW SOIC–16 D SUFFIX CASE 751B 1 16 14022B AWLYWW |
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