Philips Semiconductors

Product data

SSTV16857

14-bit SSTL_2 registered driver

with differential clock inputs

2002 Sep 27

6

TIMING REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

Clock frequency

—

200

MHz

Pulse duration, CLK, CLK HIGH or LOW

1.0

—

ns

t

Setup time

Data before CLK

↑, CLK↓

0.2

—

ns

Setup time

RESET HIGH before CLK

↑, CLK↓

0.8

—

ns

Hold time

0.75

—

ns

SWITCHING CHARACTERISTICS

LIMITS

SYMBOL

FROM

(INPUT)

TO

(OUTPUT)

UNIT

(INPUT)

(OUTPUT)

MIN

MAX

Maximum clock frequency

200

—

MHz

CLK and CLK

Q

1.0

2.8

ns

RESET

Q

2.0

4.0

ns

184/200-pin DDR SDRAM DIMM

The PLL clock distribution device and SSTV registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation

SW00686

SSTV16857

PCKV857

SSTV16857

FRONT SIDE