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X1227S8IZ-2.7A 데이터시트(PDF) 7 Page - Intersil Corporation

부품명 X1227S8IZ-2.7A
상세설명  2-Wire RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X1227S8IZ-2.7A 데이터시트(HTML) 7 Page - Intersil Corporation

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7
FN8099.1
September 15, 2005
Write Cycle Timing
Power-up Timing
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters
SCL
SDA
tWC
8th Bit of Last Byte
ACK
Stop
Condition
Start
Condition
Symbol
Parameter
Min.
Typ.(2)
Max.
Units
tPUR(1)
Time from Power-up to Read
1
ms
tPUW(1)
Time from Power-up to Write
5
ms
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC(1)
Write Cycle Time
5
10
ms
Symbols
Parameters
Min.
Typ.
Max.
Unit
VPTRIP
Programmed Reset Trip Voltage
X1227-4.5A
X1227
X1227-2.7A
X1227-2.7
4.5
4.25
2.7
2.55
4.68
4.38
2.93
2.68
4.75
4.5
3.0
2.7
V
tRPD
VCC Detect to RESET LOW
500
ns
tPURST
Power-up Reset Time-out Delay
100
200
400
ms
tF
VCC Fall Time
10
µs
tR
VCC Rise Time
10
µs
tWDO
Watchdog Timer Period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
1.7
725
225
1.75
750
250
1.8
775
275
s
ms
ms
tRST
Watchdog Reset Time-out Delay
225
250
275
ms
tRSP
2-Wire interface
1
µs
VRVALID
Reset Valid VCC
1.0
V
X1227


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