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ISL43L120IUZ 데이터시트(PDF) 10 Page - Intersil Corporation

부품명 ISL43L120IUZ
상세설명  Ultra Low ON-Resistance, Single Supply, Dual SPST Analog Switches
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제조업체  INTERSIL [Intersil Corporation]
홈페이지  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL43L120IUZ 데이터시트(HTML) 10 Page - Intersil Corporation

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10
FN6091.1
November 3, 2004
ISL43L120, ISL43L121, ISL43L122
Thin Dual Flat No-Lead Plastic Package (TDFN)
//
NX (b)
SECTION "C-C"
5
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C
0.15
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
8
7
D2
B
A
M C
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
FOR EVEN TERMINAL/SIDE
e
CL
TERMINAL TIP
L1
10 L
L8.3x3A
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.70
0.75
0.80
-
A1
-
-
0.05
-
A3
0.20 REF
-
b
0.25
0.30
0.35
5,8
D
3.00 BSC
-
D2
2.20
2.30
2.40
7,8
E
3.00 BSC
-
E2
1.40
1.50
1.60
7,8
e
0.65 BSC
-
k0.25
-
-
-
L
0.20
0.30
0.40
8
L1
-
-
0.15
1
N8
2
Nd
4
3
Rev. 2 6/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
10. COMPLIANT TO JEDEC MO-229-WEEC-1 except for
dimensions E2 & D2.


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