전자부품 데이터시트 검색엔진 |
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ISL59112 데이터시트(PDF) 3 Page - Intersil Corporation |
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ISL59112 데이터시트(HTML) 3 Page - Intersil Corporation |
3 / 6 page 3 FN6142.1 August 15, 2005 SR(hl) Negative Slew Rate VIN = 1VSTEP -80 -30 V/µs tF Fall Time 1.0VSTEP 9ns tR Rise Time 1.0VSTEP, 20% - 80% 9 ns Electrical Specifications VS+ = 3.3V, VS- = GND, TA = 25°C, RL = 150Ω to GND, unless otherwise specified (Continued) DESCRIPTION PARAMETER CONDITIONS MIN TYP MAX UNIT Typical Performance Curves FIGURE 1. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 2. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 450mW θ JA = 22 0°C /W SC 70 -6 0.5 0.4 0.3 0.2 0.1 0 0 AMBIENT TEMPERATURE (°C) 150 75 25 100 50 125 85 0.45 0.35 0.25 0.15 0.05 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 500mW 0.55 0.5 0.3 0.2 0.1 0 0 AMBIENT TEMPERATURE (°C) 150 75 25 100 50 125 85 0.4 0.45 0.25 0.15 0.05 0.35 - + - + IN RIN VDD IN EN GND VDD VDD EN=GND: SHUTDOWN IDD~0 EN=VDD: ACTIVE IDD~2.0mA VDC R6 R5 R4 R7 OUT SAG C5 C4 SYNC CLAMP SAG NETWORK AC COUPLING CAPACITOR 75 Ω 75 Ω 75 Ω CIN 100nF 47µF 22µF FIGURE 3. BLOCK DIAGRAM ISL59112 |
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